ysyx-workbench/npc/obj/Vexample___024root__Slow.cpp
tracer-ysyx a315f9ac2b > sim RTL
ysyx_22040000 李心杨
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2023-12-23 17:29:41 +08:00

24 lines
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C++

// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vexample.h for the primary calling header
#include "Vexample__pch.h"
#include "Vexample__Syms.h"
#include "Vexample___024root.h"
void Vexample___024root___ctor_var_reset(Vexample___024root* vlSelf);
Vexample___024root::Vexample___024root(Vexample__Syms* symsp, const char* v__name)
: VerilatedModule{v__name}
, vlSymsp{symsp}
{
// Reset structure values
Vexample___024root___ctor_var_reset(this);
}
void Vexample___024root::__Vconfigure(bool first) {
if (false && first) {} // Prevent unused
}
Vexample___024root::~Vexample___024root() {
}