102 lines
3.1 KiB
Makefile
102 lines
3.1 KiB
Makefile
NVBOARD_HOME ?= $(abspath ../nvboard)
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PREFIX ?= build
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CHISEL_VDIR := $(PREFIX)/chisel
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CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
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VERILATOR_FLAGS := --cc --exe
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LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image
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CHISEL_TOP_PACKAGE := learning
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CHISEL_TOP_MODULE := Main
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CHISEL_TARGET := verilog
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SUBDIRS := obj nvobj
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SUBDIRS := $(addprefix $(PREFIX),$(SUBDIRS))
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SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
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# Pretty printing
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MAKEFLAGS += --no-print-directory
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GREEN := \e[32m
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NC := \e[0m
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define colorize
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printf '$(GREEN)'$(1)'$(NC) $(2)\n'
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endef
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all: sim-bin nvboard-bin
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$(SUBDIRS):%: %/V$(CHISEL_TOP_MODULE).mk
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verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS)
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$(OBJDIR)/V$(CHISEL_TOP_MODULE): $(SUBMAKE)
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@$(call colorize,"SUBMAKE",$^)
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$(MAKE) -s -C $(dir $@) -f $< $(notdir $@)
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$(SUBMAKE): $(CPPSRCS) $(OBJDIR) chisel-src
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@$(call colorize,"VERILATOR",$@)
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verilator $(VERILATOR_FLAGS) $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) --Mdir $(abspath $(OBJDIR)) $(CHISEL_VSRC) $(CPPSRCS)
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$(OBJDIR):
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mkdir -p $@
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$(CHISEL_VDIR)/filelist.f: $(wildcard src/main/scala/*.scala)
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@$(call colorize,"CIRCT",$^)
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sbt --error "runMain circt.stage.ChiselMain --module $(CHISEL_TOP_PACKAGE).$(CHISEL_TOP_MODULE) --split-verilog --target $(CHISEL_TARGET) -td $(CHISEL_VDIR)"
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compile_commands.json: clean
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$(MAKE) $(CHISEL_VDIR)/filelist.f
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$(RM) compile_commands.json
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bear --append -- $(MAKE) nvboard-bin
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bear --append -- $(MAKE) sim-bin
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.PHONY: clean nvboard sim nvboard-bin sim-bin git_trace_sim git_trace_nvboard
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SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
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NXDC_FILES := $(abspath constr/top.nxdc)
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$(SRC_AUTO_BIND): $(NXDC_FILES)
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NVBOARD_HOME=$(NVBOARD_HOME) python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $< $@
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nvboard-bin: OBJDIR := $(PREFIX)/nvobj
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nvboard-bin: SUBMAKE := $(OBJDIR)/V$(CHISEL_TOP_MODULE).mk
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# TODO: fix this awkward way to find nvboard.a
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nvboard-bin: CPPSRCS := $(addprefix $(PWD)/,$(wildcard csrc_nvboard/*.cpp)) $(SRC_AUTO_BIND) $(NVBOARD_HOME)/build/nvboard.a
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nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags)
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nvboard-bin: $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
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@echo $(SUBMAKE) $(OBJDIR)
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sim-bin: VERILATOR_FLAGS += --trace
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sim-bin: $(CPPSRCS) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
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chisel-src: $(CHISEL_VDIR)/filelist.f
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$(eval CHISEL_VSRC := $(wildcard $(CHISEL_VDIR)/*.sv))
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@echo "GENERATED: $(CHISEL_VSRC)"
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ifneq (,$(wildcard ../Makefile))
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include ../Makefile
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else
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define git_commit # not in ICS subfolder, no tracing
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endef
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endif
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git_trace_sim:
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$(call git_commit, "sim RTL")
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git_trace_nvboard:
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$(call git_commit, "nvboard")
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nvboard: OBJDIR := $(PREFIX)/nvobj
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nvboard: nvboard-bin git_trace_nvboard
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@echo "Running NVBoard ..."
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@echo "================================"
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@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/V$(CHISEL_TOP_MODULE)
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sim: sim-bin git_trace_sim
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@echo "Running verilator sim ..."
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@echo "================================"
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@$(OBJDIR)/V$(CHISEL_TOP_MODULE)
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clean:
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$(RM) -r $(PREFIX)
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$(V).SILENT:
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