df992995ca
ysyx_22040000 李心杨 Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec 3 06:32:13 UTC 2023 x86_64 GNU/Linux 18:31:48 up 21:29, 2 users, load average: 1.18, 0.83, 0.63
7 lines
No EOL
77 B
Verilog
7 lines
No EOL
77 B
Verilog
module top(
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input a,
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input b,
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output f
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);
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assign f = a ^ b;
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endmodule |