ysyx-workbench/npc/Makefile
tracer-ysyx 3b0310ef47 > sim RTL
ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 19:50:34  up  22:48,  2 users,  load average: 0.25, 0.38, 0.46
2023-12-23 19:50:34 +08:00

25 lines
553 B
Makefile

VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
PREFIX ?= build
OBJDIR := $(PREFIX)/obj
all: $(OBJDIR)
$(MAKE) -j -C $(OBJDIR) -f Vexample.mk Vexample
sim: all
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================"
@$(OBJDIR)/Vexample
$(OBJDIR): $(VSRC) $(CPPSRC)
mkdir -p $(OBJDIR)
verilator --trace --cc --exe --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
include ../Makefile
.PHONY: clean
clean:
$(RM) -r $(OBJDIR)