ysyx-workbench/npc/vsrc/example.v
tracer-ysyx 355bd72c8d > sim RTL
ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 17:27:29  up  20:25,  2 users,  load average: 0.48, 0.77, 0.76
2023-12-23 17:27:29 +08:00

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Verilog

module our;
initial begin $display("Hello World"); $finish; end
endmodule