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refactor-npc #4

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xin wants to merge 3 commits from refactor-npc into master
pull from: refactor-npc
merge into: xin:master
Conversation 0 Commits 3 Files changed 41 +33 -493
18 changed files with 33 additions and 493 deletions
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Showing only changes of commit 5bb66edd2f - Show all commits

3
npc/CMakePresets.json
View file

@ -15,8 +15,7 @@
"ENABLE_YSYX_GIT_TRACKER": "ON",
"BUILD_CHISEL_EMIT_TARGET": "ON",
"TOPMODULE": "Flow",
"CMAKE_EXPORT_COMPILE_COMMANDS": "ON",
"BUILD_USE_BLOOP": "ON"
"CMAKE_EXPORT_COMPILE_COMMANDS": "ON"
}
}
],

4
npc/cmake/ChiselBuild.cmake
View file

@ -32,7 +32,9 @@ else()
set(CHISEL_TEST_TARGET sbt_${TOPMODULE}_test)
add_custom_command(
OUTPUT ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF}
COMMAND sbt "run ${CHISEL_EMIT_ARGS}"
# Try to use native sbt to increase performance when possible
COMMAND ${CMAKE_COMMAND} -E env SBT_NATIVE_CLIENT=true sbt
"run ${CHISEL_EMIT_ARGS}"
WORKING_DIRECTORY ${SCALA_CORE}
DEPENDS ${CHISEL_DEPENDENCY}
VERBATIM

57
npc/core/src/main/scala/components/ALU.scala
View file

@ -32,61 +32,7 @@ object ALUControlInterface {
def apply() = new ALUControlInterface;
}
class ALU[T <: UInt](tpe: T) extends Module {
import ALUControlInterface._
val control = IO(ALUControlInterface())
val in = IO(new Bundle {
val a = Input(Vec(SrcASelect.all.length, tpe))
val b = Input(Vec(SrcBSelect.all.length, tpe))
})
val out = IO(new Bundle {
val eq = Output(Bool())
val result = Output(tpe)
})
val a = in.a(control.srcASelect.asUInt)
val b = in.b(control.srcBSelect.asUInt)
// val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
val add = a + b
val sub = a - b
val and = a & b
val not = ~a
val or = a | b
val xor = a ^ b
val slt = a.asSInt < b.asSInt
val sltu = a < b
val sll = a << b(log2Ceil(tpe.getWidth), 0)
val srl = a >> b(log2Ceil(tpe.getWidth), 0)
val sra = a.asSInt >> b(log2Ceil(tpe.getWidth), 0)
out.eq := a === b
import ALUControlInterface.OpSelect._
out.result := MuxLookup(control.op, 0.U)(
Seq(
aOpAdd -> add,
aOpSub -> sub,
aOpAnd -> and,
aOpOr -> or,
aOpXor -> xor,
aOpSlt -> slt,
aOpSltu -> sltu,
aOpSll -> sll,
aOpSrl -> srl,
aOpSra -> sra.asUInt
)
)
}
object ALU {
def apply[T <: UInt](tpe: T): ALU[T] = {
Module(new ALU(tpe))
}
}
class newALU(implicit p: Params) extends Module {
class ALU(implicit p: Params) extends Module {
import ALUControlInterface._
val control = IO(ALUControlInterface())
val in = IO(new Bundle {
@ -100,7 +46,6 @@ class newALU(implicit p: Params) extends Module {
val a = in.a(control.srcASelect.asUInt)
val b = in.b(control.srcBSelect.asUInt)
// val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
val add = a + b
val sub = a - b
val and = a & b

57
npc/core/src/main/scala/components/ProgramCounter.scala
View file

@ -10,50 +10,7 @@ import flow.Params
import RV32InstSubfields._
import flow.components.util._
class PcControlInterface extends Bundle {
object SrcSelect extends ChiselEnum {
val pStaticNpc, pExeOut = Value
}
val useImmB = Input(Bool())
val srcSelect = Input(SrcSelect())
def ctrlBindPorts = {
useImmB :: srcSelect :: HNil
}
}
class ProgramCounter[T <: UInt](tpe: T) extends Module {
val control = IO(new PcControlInterface)
val in = IO(new Bundle {
val immB = Input(tpe)
val exeOut = Input(tpe)
})
val out = IO(Output(tpe))
private val pc_reg = RegInit(0x80000000L.U)
// pc := in.pcSrcs(control.srcSelect.asUInt)
import control.SrcSelect._
when(control.useImmB === true.B) {
pc_reg := pc_reg + in.immB
}.elsewhen(control.srcSelect === pStaticNpc) {
pc_reg := pc_reg + 4.U
}.elsewhen(control.srcSelect === pExeOut) {
pc_reg := in.exeOut
}
out := pc_reg
}
object ProgramCounter {
def apply[T <: UInt](tpe: T): ProgramCounter[T] = {
val pc = Module(new ProgramCounter(tpe))
pc
}
}
object newPcControlInterface {
object PcControlInterface {
object SrcSelect extends ChiselEnum {
val pStatic, pJmp, pBR = Value
}
@ -68,9 +25,9 @@ object newPcControlInterface {
def apply() = new newPcControlInterface;
}
class newProgramCounter(implicit p: Params) extends Module {
val control = IO(newPcControlInterface())
import newPcControlInterface.SrcSelect._
class ProgramCounter(implicit p: Params) extends Module {
val control = IO(PcControlInterface())
import PcControlInterface.SrcSelect._
val in = IO(new Bundle {
val brOffset = Input(UInt(p.XLEN))
val jAddr = Input(UInt(p.XLEN))
@ -96,10 +53,10 @@ class PcController(implicit p: Params) extends Module {
val inst = Input(UInt(p.instWidth))
})
val out = IO(Flipped(newPcControlInterface()))
val out = IO(Flipped(PcControlInterface()))
import RV32Inst._
import newPcControlInterface.SrcSelect._
import PcControlInterface.SrcSelect._
private val _jmpMapping = Array(jal, jalr).map(_ -> pJmp.BP)
private val _brMapping =
Array(beq, bne, blt, bge, bltu, bgeu).map(_ -> pBR.BP)
@ -109,7 +66,7 @@ class PcController(implicit p: Params) extends Module {
pStatic.BP
)
out.srcSelect := newPcControlInterface.SrcSelect
out.srcSelect := PcControlInterface.SrcSelect
.safe(
(
decoder(in.inst, mapping)

37
npc/core/src/main/scala/components/RegisterFile.scala
View file

@ -11,7 +11,6 @@ import shapeless.{HList, HNil, ::}
import flow.Params
import flow.components.util._
import flow.components.RV32Inst._
object RegControl {
object WriteSelect extends ChiselEnum {
val rAluOut, rMemOut, rNpc = Value
@ -28,39 +27,7 @@ object RegControl {
def apply() = new RegControl
}
class RegisterFile[T <: Data](tpe: T, regCount: Int, numReadPorts: Int)
extends Module {
require(numReadPorts >= 0)
val control = IO(RegControl())
val dataAddrWidth = log2Ceil(regCount).W
val in = IO(new Bundle {
val writeAddr = Input(UInt(dataAddrWidth))
val writeData = Input(Vec(RegControl.WriteSelect.all.length, tpe))
val rs = Input(Vec(numReadPorts, UInt(dataAddrWidth)))
})
val out = IO(new Bundle {
val src = Output(Vec(numReadPorts, tpe))
})
val regResetValue = 0.U(tpe.getWidth.W)
val regFile = RegInit(VecInit(Seq.fill(regCount)(regResetValue)))
val writeAddrOH = UIntToOH(in.writeAddr)
for ((reg, i) <- regFile.zipWithIndex.tail) {
reg := Mux(
writeAddrOH(i.U(log2Ceil(regCount).W)) && control.writeEnable,
in.writeData(control.writeSelect.asUInt),
reg
)
}
regFile(0) := 0.U
for (port <- 0 until numReadPorts) {
out.src(port) := regFile(in.rs(port).asUInt)
}
}
class newRegisterFile(implicit p: Params) extends Module {
class RegisterFile(implicit p: Params) extends Module {
val in = IO(new Bundle {
val rd = Input(UInt(p.regsAddrWidth))
val writeData = Input(Vec(RegControl.WriteSelect.all.length, UInt(p.XLEN)))
@ -136,8 +103,6 @@ class RegisterFileController(implicit p: Params) extends Module {
BitPat("b0")
)
println(writeEnableMapping)
out.writeSelect := RegControl.WriteSelect
.safe(
decoder(in.inst, writeSelectMapping)

6
npc/core/src/main/scala/stages/EX.scala
View file

@ -5,7 +5,7 @@ import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import flow.Params
import flow.stages.utils._
import flow.components.newALU
import flow.components.ALU
import flow.components.ALUControlInterface
import flow.stages.messages._
import flow.components.RV32InstSubfields._
@ -28,7 +28,7 @@ class EX(implicit val p: Params) extends Module {
private val _in = msgio.in.bits
private val _out = msgio.out.bits
val alu = Module(new newALU)
val alu = Module(new ALU)
alu.control := _in.aluCtrl;
{
@ -52,7 +52,7 @@ class EX(implicit val p: Params) extends Module {
_toIF.brOffset := _in.inst.immB
_toIF.pc := _in.pc
import flow.components.newPcControlInterface.SrcSelect._
import flow.components.PcControlInterface.SrcSelect._
val regSrcEq = Wire(Bool());
regSrcEq := (_in.src1 === _in.src2);
when(_in.pcCtrl.srcSelect === pBR) {

2
npc/core/src/main/scala/stages/ID.scala
View file

@ -27,7 +27,7 @@ class ID(implicit val p: Params) extends Module {
val _out = msgio.out.bits
val _fromWB = io.fromWB
val regs = Module(new newRegisterFile with InlineInstance)
val regs = Module(new RegisterFile with InlineInstance)
// Controllers
val pcController = Module(new PcController)

6
npc/core/src/main/scala/stages/IF.scala
View file

@ -2,8 +2,8 @@ package flow.stages
import chisel3._
import flow.Params
import flow.components.newProgramCounter
import flow.components.newPcControlInterface
import flow.components.ProgramCounter
import flow.components.PcControlInterface
import flow.stages.utils._
import flow.stages.messages._
import chisel3.util.DecoupledIO
@ -31,7 +31,7 @@ class IF(implicit val p: Params) extends Module {
val _fromEx = io.fromEx
// Program Counter
private val pc = Module(new newProgramCounter)
private val pc = Module(new ProgramCounter)
// PC update
pc.in.brOffset := _fromEx.brOffset

4
npc/core/src/main/scala/stages/Messages.scala
View file

@ -19,7 +19,7 @@ class ID2EX(implicit p: Params) extends Bundle {
// Control
val aluCtrl = Flipped(ALUControlInterface())
val ramCtrl = Flipped(new DpiRamControlInterface)
val pcCtrl = Flipped(newPcControlInterface())
val pcCtrl = Flipped(PcControlInterface())
val regCtrl = Flipped(RegControl())
}
@ -51,7 +51,7 @@ class EX2IF(implicit p: Params) extends Bundle {
val jAddr = UInt(p.XLEN)
// Control
val pcCtrl = Flipped(newPcControlInterface())
val pcCtrl = Flipped(PcControlInterface())
}
class IF2Ram(implicit p: Params) extends Bundle {

11
npc/core/src/main/scala/top/Config.scala
View file

@ -24,5 +24,14 @@ case class Params(
regsResetValue: BigInt = 0L,
arch: String,
csrAddrWidth: Width = 12.W,
resetVector: BigInt = BigInt(0x80000000L)
resetVector: BigInt = BigInt(0x80000000L),
csrNameToAddr: Map[String, Int] = Map(
"mstatus" -> 0x300,
"mtvec" -> 0x305,
"mie" -> 0x304,
"mepc" -> 0x341,
"mcause" -> 0x342,
"mtval" -> 0x343,
"mip" -> 0x344
)
)

60
npc/core/src/test/scala/CSR.scala
View file

@ -1,60 +0,0 @@
package flow.tests
import chisel3._
import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import chiseltest.simulator.WriteVcdAnnotation
import flow.components.CSRCore
import flow.tests.defaultParams
class CSRSpec extends AnyFreeSpec with ChiselScalatestTester {
implicit val p: flow.Params = defaultParams()
// import flow.components.CSRControlInterface
// "should compile" in {
// test(new CSRCore) { c =>
// c.clock.step(1)
// }
// }
// "Write" - {
// "delayed" in {
// test(new CSRCore) { c =>
// val tv = BigInt("deadbeef", 16)
// c.in.csrAddr.poke(c.nameToAddr("mstatus"))
// c.in.writeData.poke(tv)
// c.control.writeEnable.poke(CSRControlInterface.csrWrite.csrWriteData)
// c.clock.step(1)
//
// c.control.readEnable.poke(CSRControlInterface.csrRead.csrReadEnabled)
// c.out.readData.expect(0)
// c.out.readValid.expect(1)
//
// c.clock.step(1)
// c.out.readValid.expect(1)
// c.out.readData.expect(tv)
// }
// }
// }
//
// "Read" - {
// "controlled by readEnable" in {
// test(new CSRCore) { c =>
// val tv = BigInt("deadbeef", 16)
// c.in.csrAddr.poke(c.nameToAddr("mstatus"))
// c.in.writeData.poke(tv)
// c.control.readEnable.poke(CSRControlInterface.csrRead.csrReadEnabled)
// c.control.writeEnable.poke(CSRControlInterface.csrWrite.csrWriteData)
// c.clock.step(1)
//
// c.control.readEnable.poke(CSRControlInterface.csrRead.csrReadDisabled)
// c.out.readData.expect(0)
// c.out.readValid.expect(0)
//
// c.clock.step(1)
// c.out.readData.expect(0)
// c.out.readValid.expect(0)
// }
// }
// }
}

62
npc/core/src/test/scala/Keyboard.scala
View file

@ -1,62 +0,0 @@
package npc.keyboard
import chisel3._
import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import chiseltest.simulator.WriteVcdAnnotation
import npc.util._
class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
def transfer(keycode: Int, clock: Clock, ps2: PS2Port) : Unit = {
require(keycode >= 0 && keycode < 0xFF)
var cycle = 0
var keycode_remain = keycode << 1 // Shift 1 to do nothing at cycle 0
var keycode_collect = 0
ps2.data.poke(1)
ps2.clk.poke(true)
clock.step(1)
for (cycle <- 0 until 9) {
val last_digit = keycode_remain & 1
ps2.clk.poke(true)
ps2.data.poke(last_digit)
clock.step(32)
keycode_collect = keycode_collect | (last_digit << cycle)
keycode_remain = keycode_remain >> 1
ps2.clk.poke(false)
clock.step(32)
}
for (_ <- 9 until 11) {
ps2.clk.poke(true)
clock.step(32)
ps2.clk.poke(false)
clock.step(32)
}
assert(keycode_collect >> 1 == keycode)
clock.step(32)
}
"Simple test" in {
test(new KeyboardController).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
val data = Array(0xE4, 0xD4, 0xC4, 0xA9)
data.foreach(d => {
transfer(d, c.clock, c.io.ps2)
c.io.out.valid.expect(1.U)
c.io.out.bits.expect(d)
c.io.out.ready.poke(1)
c.clock.step(1)
c.io.out.ready.poke(0)
})
data.foreach(d => {
transfer(d, c.clock, c.io.ps2)
})
data.foreach(d => {
c.io.out.valid.expect(1.U)
c.io.out.bits.expect(d)
c.io.out.ready.poke(1)
c.clock.step(1)
c.io.out.ready.poke(0)
})
}
}
}

31
npc/core/src/test/scala/Main.scala
View file

@ -1,31 +0,0 @@
package flow
import chisel3._
import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import chiseltest.simulator.WriteVcdAnnotation
import flow.stages._
import flow.Params
import flow.Flow
import flow.tests.defaultParams
import flow.stages.messages._
class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
"IF" - {
implicit val p: Params = defaultParams()
class TestIF extends Module {
val IF = Module(new IF)
val io = IO(new Bundle {
val out = Output(new IF2ID)
})
io.out := IF.msgio.out
IF.msgio.out.ready := DontCare
IF.io.fromRam := DontCare
IF.io.fromEx := DontCare
}
"should compile" in {
test(new TestIF) { c => }
}
}
}

24
npc/core/src/test/scala/ProgramCounter.scala
View file

@ -1,24 +0,0 @@
package flow.tests
import chisel3._
import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import flow.components._
class ProgramCounterSpec extends AnyFreeSpec with ChiselScalatestTester {
implicit val p: flow.Params = defaultParams()
"should compile" in {
test(new newProgramCounter) { c =>
c.clock.step(1)
}
}
"Static next pc" in {
test(new newProgramCounter) { c =>
import flow.components.newPcControlInterface.SrcSelect._
c.control.srcSelect.poke(pStatic)
c.clock.step(1)
c.out.expect(p.resetVector + 4)
}
}
}

81
npc/core/src/test/scala/RegisterFile.scala
View file

@ -1,81 +0,0 @@
// package flow
// import chisel3._
// import chiseltest._
// import org.scalatest.freespec.AnyFreeSpec
// import chiseltest.simulator.WriteVcdAnnotation
// import flow.components._
// class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
// "RegisterFileCore" - {
// "register 0 is always 0" in {
// test(new RegisterFileCore(32, UInt(32.W), 2)) { c =>
// c.readPorts(0).addr.poke(0)
// c.readPorts(1).addr.poke(0)
// c.writePort.enable.poke(true)
// c.writePort.addr.poke(0)
// c.writePort.data.poke(0x1234)
// c.readPorts(0).data.expect(0)
// c.readPorts(1).data.expect(0)
// c.clock.step(2)
// c.readPorts(0).data.expect(0)
// c.readPorts(1).data.expect(0)
// }
// }
// "register other than 0 can be written" in {
// test(new RegisterFileCore(32, UInt(32.W), 2)) { c =>
// import scala.util.Random
// val r = new Random()
// for (i <- 1 until 32) {
// val v = r.nextLong() & 0xFFFFFFFFL
// c.readPorts(0).addr.poke(i)
// c.writePort.enable.poke(true)
// c.writePort.addr.poke(i)
// c.writePort.data.poke(v)
// c.clock.step(1)
// c.readPorts(0).data.expect(v)
// }
// }
// }
// }
// "RegisterInterface" - {
// class Top extends Module {
// val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2))
// val rf = RegisterFile(32, UInt(32.W), 2, 2)
// io :<>= rf
// }
// "write" in {
// test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
// import c.io.control.WriteSelect._
// val writePort = rAluOut.litValue.toInt
// c.io.control.writeEnable.poke(true)
// c.io.control.writeSelect.poke(rAluOut)
// c.io.in.writeAddr.poke(5)
// c.io.in.writeData(writePort).poke(0xcdef)
// c.io.in.rs(0).poke(5)
// c.clock.step(1)
// c.io.out.src(0).expect(0xcdef)
// }
// }
// "no data is written when not enabled" in {
// test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
// import c.io.control.WriteSelect._
// val writePort = rAluOut.litValue.toInt
// c.io.control.writeEnable.poke(true)
// c.io.control.writeSelect.poke(rAluOut)
// c.io.in.writeAddr.poke(5)
// c.io.in.writeData(writePort).poke(0xcdef)
// c.io.in.rs(0).poke(5)
// c.clock.step(1)
// c.io.control.writeEnable.poke(false)
// c.io.in.writeData(writePort).poke(0x1234)
// c.clock.step(1)
// c.io.out.src(0).expect(0xcdef)
// }
// }
// }
// }

70
npc/core/src/test/scala/StageConnect.scala
View file

@ -1,70 +0,0 @@
package flow.tests
import chisel3._
import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import chiseltest.simulator.WriteVcdAnnotation
import flow.tests.defaultParams
import flow.stages.utils._
import flow.stages.DecoupledMsgIO
import chisel3.util.Decoupled
class StageConnect extends AnyFreeSpec with ChiselScalatestTester {
"should compile" in {
implicit val p: flow.Params = defaultParams().copy(arch = "single")
class stage1 extends Module {
val io = DecoupledMsgIO(out = (new Bundle {
val data = UInt(12.W)
}).S)
io.out.valid := true.B
io.out.bits.data := 1.U
}
class stage2 extends Module {
val io = DecoupledMsgIO(Some(new Bundle {
val data = UInt(12.W)
}))
io.in.ready := true.B
}
class stage3 extends Module {
val wireOut = DecoupledMsgIO(
out = Some(new Bundle {
val data = UInt(12.W)
}),
isIO = false
)
val wireIn = DecoupledMsgIO(
Some(new Bundle {
val data = UInt(12.W)
}),
isIO = false
)
wireOut connect [Nothing] wireIn
wireOut.out.valid := true.B
wireOut.out.bits.data := 1.U
wireIn.in.ready := true.B
}
class stage extends Module {
val s1 = Module(new stage1)
val s2 = Module(new stage2)
s1.io connect [Nothing] s2.io
}
import circt.stage.ChiselStage
println(ChiselStage.emitSystemVerilog(new stage1))
test(new stage) { c =>
println(c)
}
test(new stage3) { c =>
println(c)
}
}
}

8
npc/core/src/test/scala/params.scala
View file

@ -1,8 +0,0 @@
package flow.tests
import chisel3._
import flow.Params
object defaultParams {
def apply(): Params = new Params(XLEN = 32.W, arch = "single")
}

3
npc/flake.nix
View file

@ -55,9 +55,8 @@
nvboard
flow
espresso
bloop
coursier
sbt
sbt-with-scala-native
gef
] ++ [stablePkgs.verilator];
CHISEL_FIRTOOL_PATH = "${nixpkgs-circt162.legacyPackages.${system}.circt}/bin";