Add difftest support to npc #3
43 changed files with 1319 additions and 501 deletions
4
.clang-format
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4
.clang-format
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@ -0,0 +1,4 @@
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---
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Language: Cpp
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BasedOnStyle: LLVM
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ReflowComments: false
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45
.gitea/workflows/npc-test.yml
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45
.gitea/workflows/npc-test.yml
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@ -0,0 +1,45 @@
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name: Run CTests within npc
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on: [push]
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jobs:
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npc-test:
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runs-on: nix
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steps:
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- uses: https://github.com/cachix/cachix-action@v14
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with:
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name: ysyx
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authToken: '${{ secrets.CACHIX_SIGNING_KEY }}'
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- uses: actions/checkout@v4
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with:
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submodules: true
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- name: Cache develop environment
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id: cache-nix-develop
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uses: actions/cache@v4
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with:
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path: /nix/store
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key: nix-develop-${{ hashFiles('flake.*') }}
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- name: Fetch nix store
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if: steps.cache-nix-develop.outputs.cache-hit != 'true'
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run: nix develop .#npc
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- name: Use develop environment
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uses: https://git.xinyang.life/xin/nix-develop@main
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with:
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arguments: .#npc
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- name: Cache sbt dependencies
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id: cache-sbt-dependency
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uses: actions/cache@v4
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with:
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path: npc/core
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key: core-${{ hashFiles('npc/core/build.sbt') }}
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- name: Fetch sbt dependencies
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if: steps.cache-sbt-dependency.outputs.cache-hit != 'true'
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run: |
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cd npc/core
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sbt update
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- name: Run difftests
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run: |
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mkdir -p npc/build
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cd npc/build
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cmake $cmakeFlags ../
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make -j8
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ctest -V
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1
.gitignore
vendored
1
.gitignore
vendored
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@ -12,3 +12,4 @@
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/nvboard
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/nvboard
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**/.cache
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**/.cache
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**/result
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**/result
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/.pre-commit-config.yaml
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151
flake.lock
151
flake.lock
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@ -1,5 +1,21 @@
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{
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{
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"nodes": {
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"nodes": {
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"flake-compat": {
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"flake": false,
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"locked": {
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"lastModified": 1696426674,
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"narHash": "sha256-kvjfFW7WAETZlt09AgDn1MrtKzP7t90Vf7vypd3OL1U=",
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"owner": "edolstra",
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"repo": "flake-compat",
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"rev": "0f9255e01c2351cc7d116c072cb317785dd33b33",
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"type": "github"
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},
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"original": {
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"owner": "edolstra",
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"repo": "flake-compat",
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"type": "github"
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}
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},
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"flake-utils": {
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"flake-utils": {
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"inputs": {
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"inputs": {
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"systems": "systems"
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"systems": "systems"
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@ -18,6 +34,45 @@
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"type": "github"
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"type": "github"
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}
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}
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},
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},
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"flake-utils_2": {
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"inputs": {
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"systems": "systems_2"
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},
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"locked": {
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"lastModified": 1710146030,
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"narHash": "sha256-SZ5L6eA7HJ/nmkzGG7/ISclqe6oZdOZTNoesiInkXPQ=",
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"owner": "numtide",
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"repo": "flake-utils",
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"rev": "b1d9ab70662946ef0850d488da1c9019f3a9752a",
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"type": "github"
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},
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"original": {
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"owner": "numtide",
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"repo": "flake-utils",
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"type": "github"
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}
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},
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"gitignore": {
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"inputs": {
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"nixpkgs": [
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"pre-commit-hooks",
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"nixpkgs"
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]
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},
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"locked": {
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"lastModified": 1709087332,
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"narHash": "sha256-HG2cCnktfHsKV0s4XW83gU3F57gaTljL9KNSuG6bnQs=",
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"owner": "hercules-ci",
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"repo": "gitignore.nix",
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"rev": "637db329424fd7e46cf4185293b9cc8c88c95394",
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"type": "github"
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},
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"original": {
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"owner": "hercules-ci",
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"repo": "gitignore.nix",
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"type": "github"
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}
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},
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"nixpkgs": {
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"nixpkgs": {
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"locked": {
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"locked": {
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"lastModified": 1709237383,
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"lastModified": 1709237383,
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@ -34,10 +89,89 @@
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"type": "github"
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"type": "github"
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}
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}
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},
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},
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"nixpkgs-circt162": {
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"locked": {
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"lastModified": 1705645507,
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"narHash": "sha256-tX3vipIAmNDBA8WNWG4oY4KyTfnm2YieTHO2BhG8ISA=",
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"owner": "NixOS",
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"repo": "nixpkgs",
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"rev": "7995cae3ad60e3d6931283d650d7f43d31aaa5c7",
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"type": "github"
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},
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"original": {
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"owner": "NixOS",
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"repo": "nixpkgs",
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"rev": "7995cae3ad60e3d6931283d650d7f43d31aaa5c7",
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"type": "github"
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}
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},
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"nixpkgs-stable": {
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"locked": {
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"lastModified": 1710695816,
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"narHash": "sha256-3Eh7fhEID17pv9ZxrPwCLfqXnYP006RKzSs0JptsN84=",
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"owner": "NixOS",
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"repo": "nixpkgs",
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"rev": "614b4613980a522ba49f0d194531beddbb7220d3",
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"type": "github"
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},
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"original": {
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"owner": "NixOS",
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"ref": "nixos-23.11",
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"repo": "nixpkgs",
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"type": "github"
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}
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},
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"nur-xin": {
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"inputs": {
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"nixpkgs": [
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"nixpkgs"
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]
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},
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"locked": {
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"lastModified": 1710242657,
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"narHash": "sha256-tgaILHKZH6vC8P8N8NBMNQ/XIpTY72zMojlGLPLPLZk=",
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"ref": "refs/heads/master",
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"rev": "6a499c8371c6a14d11a8c2fcc9f233e7b8e688a0",
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"revCount": 148,
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"type": "git",
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"url": "https://git.xinyang.life/xin/nur.git"
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},
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"original": {
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"type": "git",
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"url": "https://git.xinyang.life/xin/nur.git"
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}
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},
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"pre-commit-hooks": {
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"inputs": {
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"flake-compat": "flake-compat",
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"flake-utils": "flake-utils_2",
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"gitignore": "gitignore",
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"nixpkgs": [
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"nixpkgs"
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],
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"nixpkgs-stable": "nixpkgs-stable"
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},
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"locked": {
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"lastModified": 1712055707,
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"narHash": "sha256-4XLvuSIDZJGS17xEwSrNuJLL7UjDYKGJSbK1WWX2AK8=",
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"owner": "cachix",
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"repo": "pre-commit-hooks.nix",
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"rev": "e35aed5fda3cc79f88ed7f1795021e559582093a",
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"type": "github"
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},
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"original": {
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"owner": "cachix",
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"repo": "pre-commit-hooks.nix",
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"type": "github"
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}
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},
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"root": {
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"root": {
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"inputs": {
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"inputs": {
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"flake-utils": "flake-utils",
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"flake-utils": "flake-utils",
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"nixpkgs": "nixpkgs"
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"nixpkgs": "nixpkgs",
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"nixpkgs-circt162": "nixpkgs-circt162",
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"nur-xin": "nur-xin",
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"pre-commit-hooks": "pre-commit-hooks"
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}
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}
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},
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},
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"systems": {
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"systems": {
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@ -54,6 +188,21 @@
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"repo": "default",
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"repo": "default",
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"type": "github"
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"type": "github"
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}
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}
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},
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"systems_2": {
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"locked": {
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"lastModified": 1681028828,
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"narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=",
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"owner": "nix-systems",
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"repo": "default",
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"rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e",
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"type": "github"
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},
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"original": {
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"owner": "nix-systems",
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"repo": "default",
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"type": "github"
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}
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}
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}
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},
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},
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"root": "root",
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"root": "root",
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70
flake.nix
70
flake.nix
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@ -1,13 +1,30 @@
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{
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{
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inputs = {
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inputs = {
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nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
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nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
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nixpkgs-circt162.url = "github:NixOS/nixpkgs/7995cae3ad60e3d6931283d650d7f43d31aaa5c7";
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flake-utils.url = "github:numtide/flake-utils";
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flake-utils.url = "github:numtide/flake-utils";
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pre-commit-hooks = {
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url = "github:cachix/pre-commit-hooks.nix";
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inputs.nixpkgs.follows = "nixpkgs";
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};
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nur-xin = {
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url = "git+https://git.xinyang.life/xin/nur.git";
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inputs.nixpkgs.follows = "nixpkgs";
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};
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};
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};
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outputs = { self, ... }@inputs: with inputs;
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outputs = { self, ... }@inputs: with inputs;
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flake-utils.lib.eachDefaultSystem (system:
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flake-utils.lib.eachDefaultSystem (system:
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let
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let
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pkgs = nixpkgs.legacyPackages.${system};
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pkgs = import nixpkgs {
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inherit system;
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config.allowUnfree = true;
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overlays = [
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(self: super: {
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nvboard = nur-xin.legacyPackages.${system}.nvboard;
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})
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];
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};
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crossPkgs = import nixpkgs {
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crossPkgs = import nixpkgs {
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localSystem = system;
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localSystem = system;
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crossSystem = {
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crossSystem = {
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@ -20,7 +37,20 @@
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};
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};
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in
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in
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{
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{
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checks = {
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pre-commit-check = pre-commit-hooks.lib.${system}.run {
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src = ./.;
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hooks = {
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trim-trailing-whitespace.enable = true;
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clang-format = {
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enable = true;
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types_or = pkgs.lib.mkForce [ "c" "c++" ];
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};
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};
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};
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};
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packages.nemu = pkgs.callPackage ./nemu { am-kernels = self.packages.${system}.am-kernels; };
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packages.nemu = pkgs.callPackage ./nemu { am-kernels = self.packages.${system}.am-kernels; };
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packages.nemu-lib = pkgs.callPackage ./nemu { am-kernels = self.packages.${system}.am-kernels; defconfig = "riscv32-lib_defconfig"; };
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packages.abstract-machine = crossPkgs.callPackage ./abstract-machine { isa = "riscv"; platform = "nemu"; };
|
packages.abstract-machine = crossPkgs.callPackage ./abstract-machine { isa = "riscv"; platform = "nemu"; };
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|
|
||||||
packages.am-kernels = crossPkgs.stdenv.mkDerivation rec {
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packages.am-kernels = crossPkgs.stdenv.mkDerivation rec {
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@ -53,6 +83,44 @@
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inputsFrom = [
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inputsFrom = [
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self.packages.${system}.nemu
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self.packages.${system}.nemu
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||||||
];
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];
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IMAGES_PATH = "${self.packages.${system}.am-kernels}/share/binary";
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||||||
|
};
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||||||
|
|
||||||
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devShells.npc = with pkgs; mkShell {
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|
inherit (self.checks.${system}.pre-commit-check) shellHook;
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CHISEL_FIRTOOL_PATH = "${nixpkgs-circt162.legacyPackages.${system}.circt}/bin";
|
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|
packages = [
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||||||
|
clang-tools
|
||||||
|
cmake
|
||||||
|
ninja
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||||||
|
coursier
|
||||||
|
espresso
|
||||||
|
bloop
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||||||
|
|
||||||
|
gdb
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||||||
|
jre
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||||||
|
|
||||||
|
gtkwave
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||||||
|
];
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||||||
|
|
||||||
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nativeBuildInputs = [
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|
cmake
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|
sbt
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||||||
|
nvboard
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||||||
|
nixpkgs-circt162.legacyPackages.${system}.circt
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||||||
|
yosys
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||||||
|
cli11
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||||||
|
];
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|
|
||||||
|
buildInputs = [
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|
verilator
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||||||
|
nvboard
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||||||
|
openssl
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||||||
|
] ++ self.checks.${system}.pre-commit-check.enabledPackages;
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||||||
|
|
||||||
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cmakeFlags = [
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||||||
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"-DDIFFTEST_LIB:string=${self.packages.${system}.nemu-lib}/lib/riscv32-nemu-interpreter-so"
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||||||
|
];
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
);
|
);
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||||||
|
|
|
||||||
|
|
@ -1,3 +0,0 @@
|
||||||
---
|
|
||||||
Language: Cpp
|
|
||||||
BasedOnStyle: LLVM
|
|
||||||
20
nemu/Kconfig
20
nemu/Kconfig
|
|
@ -126,6 +126,26 @@ endmenu
|
||||||
|
|
||||||
menu "Testing and Debugging"
|
menu "Testing and Debugging"
|
||||||
|
|
||||||
|
choice
|
||||||
|
prompt "Choose log level"
|
||||||
|
default LOG_TRACE
|
||||||
|
config LOG_TRACE
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||||||
|
bool "trace"
|
||||||
|
config LOG_INFO
|
||||||
|
bool "info"
|
||||||
|
config LOG_WARNING
|
||||||
|
bool "warning"
|
||||||
|
config LOG_ERROR
|
||||||
|
bool "error"
|
||||||
|
endchoice
|
||||||
|
|
||||||
|
config LOG_LEVEL
|
||||||
|
int
|
||||||
|
default 1 if LOG_ERROR
|
||||||
|
default 2 if LOG_WARNING
|
||||||
|
default 3 if LOG_INFO
|
||||||
|
default 4 if LOG_TRACE
|
||||||
|
default 0
|
||||||
|
|
||||||
config TRACE
|
config TRACE
|
||||||
bool "Enable tracer"
|
bool "Enable tracer"
|
||||||
|
|
|
||||||
72
nemu/configs/riscv32-lib_defconfig
Normal file
72
nemu/configs/riscv32-lib_defconfig
Normal file
|
|
@ -0,0 +1,72 @@
|
||||||
|
#
|
||||||
|
# Automatically generated file; DO NOT EDIT.
|
||||||
|
# NEMU Configuration Menu
|
||||||
|
#
|
||||||
|
# CONFIG_ISA_x86 is not set
|
||||||
|
# CONFIG_ISA_mips32 is not set
|
||||||
|
CONFIG_ISA_riscv=y
|
||||||
|
# CONFIG_ISA_loongarch32r is not set
|
||||||
|
CONFIG_ISA="riscv32"
|
||||||
|
|
||||||
|
#
|
||||||
|
# ISA-dependent Options for riscv
|
||||||
|
#
|
||||||
|
# CONFIG_RV64 is not set
|
||||||
|
# CONFIG_RVE is not set
|
||||||
|
# end of ISA-dependent Options for riscv
|
||||||
|
|
||||||
|
CONFIG_ENGINE_INTERPRETER=y
|
||||||
|
CONFIG_ENGINE="interpreter"
|
||||||
|
CONFIG_MODE_SYSTEM=y
|
||||||
|
# CONFIG_TARGET_NATIVE_ELF is not set
|
||||||
|
CONFIG_TARGET_SHARE=y
|
||||||
|
# CONFIG_TARGET_AM is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Build Options
|
||||||
|
#
|
||||||
|
CONFIG_CC_GCC=y
|
||||||
|
# CONFIG_CC_GPP is not set
|
||||||
|
# CONFIG_CC_CLANG is not set
|
||||||
|
CONFIG_CC="gcc"
|
||||||
|
# CONFIG_CC_O0 is not set
|
||||||
|
# CONFIG_CC_O1 is not set
|
||||||
|
CONFIG_CC_O2=y
|
||||||
|
# CONFIG_CC_O3 is not set
|
||||||
|
CONFIG_CC_OPT="-O2"
|
||||||
|
CONFIG_CC_LTO=y
|
||||||
|
CONFIG_CC_DEBUG=y
|
||||||
|
# CONFIG_CC_ASAN is not set
|
||||||
|
# end of Build Options
|
||||||
|
|
||||||
|
#
|
||||||
|
# Testing and Debugging
|
||||||
|
#
|
||||||
|
CONFIG_LOG_TRACE=y
|
||||||
|
# CONFIG_LOG_INFO is not set
|
||||||
|
# CONFIG_LOG_WARNING is not set
|
||||||
|
# CONFIG_LOG_ERROR is not set
|
||||||
|
CONFIG_LOG_LEVEL=4
|
||||||
|
# CONFIG_TRACE is not set
|
||||||
|
CONFIG_DIFFTEST_REF_PATH="none"
|
||||||
|
CONFIG_DIFFTEST_REF_NAME="none"
|
||||||
|
# end of Testing and Debugging
|
||||||
|
|
||||||
|
#
|
||||||
|
# Memory Configuration
|
||||||
|
#
|
||||||
|
CONFIG_MBASE=0x80000000
|
||||||
|
CONFIG_MSIZE=0x8000000
|
||||||
|
CONFIG_PC_RESET_OFFSET=0
|
||||||
|
# CONFIG_PMEM_MALLOC is not set
|
||||||
|
CONFIG_PMEM_GARRAY=y
|
||||||
|
CONFIG_MEM_RANDOM=y
|
||||||
|
# end of Memory Configuration
|
||||||
|
|
||||||
|
#
|
||||||
|
# Miscellaneous
|
||||||
|
#
|
||||||
|
CONFIG_TIMER_GETTIMEOFDAY=y
|
||||||
|
# CONFIG_TIMER_CLOCK_GETTIME is not set
|
||||||
|
CONFIG_RT_CHECK=y
|
||||||
|
# end of Miscellaneous
|
||||||
|
|
@ -2,7 +2,8 @@
|
||||||
lib,
|
lib,
|
||||||
stdenv,
|
stdenv,
|
||||||
am-kernels,
|
am-kernels,
|
||||||
dtc
|
dtc,
|
||||||
|
defconfig ? "alldefconfig",
|
||||||
}:
|
}:
|
||||||
|
|
||||||
stdenv.mkDerivation rec {
|
stdenv.mkDerivation rec {
|
||||||
|
|
@ -31,27 +32,27 @@ stdenv.mkDerivation rec {
|
||||||
|
|
||||||
configurePhase = ''
|
configurePhase = ''
|
||||||
export NEMU_HOME=$(pwd)
|
export NEMU_HOME=$(pwd)
|
||||||
make alldefconfig
|
make ${defconfig}
|
||||||
'';
|
'';
|
||||||
|
|
||||||
buildPhase = ''
|
buildPhase = ''
|
||||||
make
|
make
|
||||||
'';
|
'';
|
||||||
|
|
||||||
doCheck = true;
|
doCheck = (defconfig == "alldefconfig");
|
||||||
checkPhase = ''
|
checkPhase = if doCheck then ''
|
||||||
export IMAGES_PATH=${am-kernels}/share/binary
|
export IMAGES_PATH=${am-kernels}/share/binary
|
||||||
make test
|
make test
|
||||||
'';
|
'' else "";
|
||||||
|
|
||||||
installPhase = ''
|
installPhase = ''
|
||||||
mkdir -p $out/bin
|
mkdir -p $out/bin
|
||||||
|
mkdir -p $out/lib
|
||||||
make PREFIX=$out install
|
make PREFIX=$out install
|
||||||
'';
|
'';
|
||||||
|
|
||||||
shellHook = ''
|
shellHook = ''
|
||||||
export NEMU_HOME=$(pwd)
|
export NEMU_HOME=$(pwd)
|
||||||
export IMAGES_PATH=${am-kernels}/share/binary
|
|
||||||
'';
|
'';
|
||||||
|
|
||||||
meta = with lib; {
|
meta = with lib; {
|
||||||
|
|
|
||||||
|
|
@ -16,32 +16,50 @@
|
||||||
#ifndef __DEBUG_H__
|
#ifndef __DEBUG_H__
|
||||||
#define __DEBUG_H__
|
#define __DEBUG_H__
|
||||||
|
|
||||||
|
#include <macro.h>
|
||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
#include <utils.h>
|
#include <utils.h>
|
||||||
#include <macro.h>
|
|
||||||
|
|
||||||
IFDEF(CONFIG_ITRACE, void log_itrace_print());
|
IFDEF(CONFIG_ITRACE, void log_itrace_print());
|
||||||
|
|
||||||
#define Trace(format, ...) \
|
#if (CONFIG_LOG_LEVEL >= 4)
|
||||||
_Log("[TRACE] " format "\n", ## __VA_ARGS__)
|
#define Trace(format, ...) _Log("[TRACE] " format "\n", ##__VA_ARGS__)
|
||||||
|
#else
|
||||||
|
#define Trace(format, ...)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_LOG_LEVEL >= 3)
|
||||||
#define Log(format, ...) \
|
#define Log(format, ...) \
|
||||||
_Log(ANSI_FMT("[INFO] %s:%d %s() ", ANSI_FG_BLUE) format "\n", \
|
_Log(ANSI_FMT("[INFO] %s:%d %s() ", ANSI_FG_BLUE) format "\n", __FILE__, \
|
||||||
__FILE__, __LINE__, __func__, ## __VA_ARGS__)
|
__LINE__, __func__, ##__VA_ARGS__)
|
||||||
|
#else
|
||||||
|
#define Log(format, ...)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_LOG_LEVEL >= 2)
|
||||||
#define Warning(format, ...) \
|
#define Warning(format, ...) \
|
||||||
_Log(ANSI_FMT("[WARNING] %s:%d %s() ", ANSI_FG_YELLOW) format "\n", \
|
_Log(ANSI_FMT("[WARNING] %s:%d %s() ", ANSI_FG_YELLOW) format "\n", \
|
||||||
__FILE__, __LINE__, __func__, ##__VA_ARGS__)
|
__FILE__, __LINE__, __func__, ##__VA_ARGS__)
|
||||||
|
#else
|
||||||
|
#define Warning(format, ...)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_LOG_LEVEL >= 1)
|
||||||
#define Error(format, ...) \
|
#define Error(format, ...) \
|
||||||
_Log(ANSI_FMT("[ERROR] %s:%d %s() ", ANSI_FG_RED) format "\n", \
|
_Log(ANSI_FMT("[ERROR] %s:%d %s() ", ANSI_FG_RED) format "\n", __FILE__, \
|
||||||
__FILE__, __LINE__, __func__, ## __VA_ARGS__)
|
__LINE__, __func__, ##__VA_ARGS__)
|
||||||
|
#else
|
||||||
|
#define Error(format, ...)
|
||||||
|
#endif
|
||||||
|
|
||||||
#define Assert(cond, format, ...) \
|
#define Assert(cond, format, ...) \
|
||||||
do { \
|
do { \
|
||||||
if (!(cond)) { \
|
if (!(cond)) { \
|
||||||
MUXDEF(CONFIG_TARGET_AM, printf(ANSI_FMT(format, ANSI_FG_RED) "\n", ## __VA_ARGS__), \
|
MUXDEF( \
|
||||||
(fflush(stdout), fprintf(stderr, ANSI_FMT(format, ANSI_FG_RED) "\n", ## __VA_ARGS__))); \
|
CONFIG_TARGET_AM, \
|
||||||
|
printf(ANSI_FMT(format, ANSI_FG_RED) "\n", ##__VA_ARGS__), \
|
||||||
|
(fflush(stdout), fprintf(stderr, ANSI_FMT(format, ANSI_FG_RED) "\n", \
|
||||||
|
##__VA_ARGS__))); \
|
||||||
IFNDEF(CONFIG_TARGET_AM, extern FILE *log_fp; fflush(log_fp)); \
|
IFNDEF(CONFIG_TARGET_AM, extern FILE *log_fp; fflush(log_fp)); \
|
||||||
IFDEF(CONFIG_ITRACE, log_itrace_print()); \
|
IFDEF(CONFIG_ITRACE, log_itrace_print()); \
|
||||||
extern void assert_fail_msg(); \
|
extern void assert_fail_msg(); \
|
||||||
|
|
|
||||||
|
|
@ -76,8 +76,13 @@ $(BINARY):: $(OBJS) $(ARCHIVES)
|
||||||
@$(LD) -o $@ $(OBJS) $(LDFLAGS) $(ARCHIVES) $(LIBS)
|
@$(LD) -o $@ $(OBJS) $(LDFLAGS) $(ARCHIVES) $(LIBS)
|
||||||
|
|
||||||
install: $(BINARY)
|
install: $(BINARY)
|
||||||
|
ifeq ($(SHARE),1)
|
||||||
|
@mkdir -p $(PREFIX)/lib
|
||||||
|
@cp $(BINARY) $(PREFIX)/lib/
|
||||||
|
else
|
||||||
@mkdir -p $(PREFIX)/bin
|
@mkdir -p $(PREFIX)/bin
|
||||||
@cp $(BINARY) $(PREFIX)/bin/
|
@cp $(BINARY) $(PREFIX)/bin/
|
||||||
|
endif
|
||||||
|
|
||||||
clean:
|
clean:
|
||||||
-rm -rf $(BUILD_DIR)
|
-rm -rf $(BUILD_DIR)
|
||||||
|
|
|
||||||
|
|
@ -83,7 +83,7 @@ static void execute(uint64_t n) {
|
||||||
g_nr_guest_inst ++;
|
g_nr_guest_inst ++;
|
||||||
trace_and_difftest(&s, cpu.pc);
|
trace_and_difftest(&s, cpu.pc);
|
||||||
if (wp_eval_all()) {
|
if (wp_eval_all()) {
|
||||||
puts(logbuf[logbuf_rear]);
|
IFDEF(CONFIG_ITRACE, puts(logbuf[logbuf_rear]));
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (nemu_state.state != NEMU_RUNNING) break;
|
if (nemu_state.state != NEMU_RUNNING) break;
|
||||||
|
|
@ -132,7 +132,7 @@ void cpu_exec(uint64_t n) {
|
||||||
ANSI_FMT("HIT BAD TRAP", ANSI_FG_RED))),
|
ANSI_FMT("HIT BAD TRAP", ANSI_FG_RED))),
|
||||||
nemu_state.halt_pc);
|
nemu_state.halt_pc);
|
||||||
if(nemu_state.halt_ret != 0) {
|
if(nemu_state.halt_ret != 0) {
|
||||||
log_itrace_print();
|
IFDEF(CONFIG_ITRACE, log_itrace_print());
|
||||||
}
|
}
|
||||||
} // fall through
|
} // fall through
|
||||||
case NEMU_QUIT: statistic();
|
case NEMU_QUIT: statistic();
|
||||||
|
|
|
||||||
|
|
@ -13,25 +13,34 @@
|
||||||
* See the Mulan PSL v2 for more details.
|
* See the Mulan PSL v2 for more details.
|
||||||
***************************************************************************************/
|
***************************************************************************************/
|
||||||
|
|
||||||
#include <isa.h>
|
#include "types.h"
|
||||||
#include <cpu/cpu.h>
|
#include <cpu/cpu.h>
|
||||||
|
#include <cpu/decode.h>
|
||||||
#include <difftest-def.h>
|
#include <difftest-def.h>
|
||||||
|
#include <isa.h>
|
||||||
#include <memory/paddr.h>
|
#include <memory/paddr.h>
|
||||||
|
|
||||||
__EXPORT void difftest_memcpy(paddr_t addr, void *buf, size_t n, bool direction) {
|
__EXPORT void difftest_memcpy(paddr_t addr, void *buf, size_t n,
|
||||||
|
bool direction) {
|
||||||
|
if (direction == DIFFTEST_TO_REF) {
|
||||||
|
memcpy(guest_to_host(addr), buf, n);
|
||||||
|
} else {
|
||||||
assert(0);
|
assert(0);
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
__EXPORT void difftest_regcpy(void *dut, bool direction) {
|
__EXPORT void difftest_regcpy(void *dut, bool direction) {
|
||||||
assert(0);
|
// assert(0);
|
||||||
|
if (direction == DIFFTEST_TO_DUT)
|
||||||
|
memcpy(dut, &cpu, sizeof(CPU_state));
|
||||||
|
else
|
||||||
|
memcpy(&cpu, dut, sizeof(CPU_state));
|
||||||
}
|
}
|
||||||
|
|
||||||
__EXPORT void difftest_exec(uint64_t n) {
|
__EXPORT void difftest_exec(uint64_t n) { cpu_exec(n); }
|
||||||
assert(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
__EXPORT void difftest_raise_intr(word_t NO) {
|
__EXPORT void difftest_raise_intr(word_t NO) {
|
||||||
assert(0);
|
// assert(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
__EXPORT void difftest_init(int port) {
|
__EXPORT void difftest_init(int port) {
|
||||||
|
|
|
||||||
|
|
@ -1 +1 @@
|
||||||
use flake
|
use flake ..#npc
|
||||||
|
|
|
||||||
1
npc/.gitignore
vendored
1
npc/.gitignore
vendored
|
|
@ -15,3 +15,4 @@ hs_err_pid*
|
||||||
.vscode/
|
.vscode/
|
||||||
.direnv/
|
.direnv/
|
||||||
compile_commands.json
|
compile_commands.json
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,91 +1,69 @@
|
||||||
cmake_minimum_required(VERSION 3.20)
|
cmake_minimum_required(VERSION 3.26)
|
||||||
|
|
||||||
project(flow)
|
project(flow)
|
||||||
set (CMAKE_CXX_STANDARD 11)
|
set (CMAKE_CXX_STANDARD 17)
|
||||||
cmake_policy(SET CMP0144 NEW)
|
cmake_policy(SET CMP0144 NEW)
|
||||||
|
|
||||||
|
include(CMakeDependentOption)
|
||||||
|
include(CTest)
|
||||||
|
enable_testing()
|
||||||
|
list(APPEND CMAKE_MODULE_PATH ${PROJECT_SOURCE_DIR}/cmake)
|
||||||
|
|
||||||
|
# -- Build options
|
||||||
|
option(BUILD_USE_BLOOP "Whether to use bloop to speed up elaborate" ON)
|
||||||
|
option(BUILD_SIM_TARGET "Whether to build verilator simulation binary" ON)
|
||||||
|
cmake_dependent_option(BUILD_SIM_NVBOARD_TARGET "Whether to build nvboard target" OFF "BUILD_SIM_TARGET" OFF)
|
||||||
|
option(ENABLE_YSYX_GIT_TRACKER "Ysyx tracker support" OFF)
|
||||||
|
set(TOPMODULE "Flow" CACHE STRING "Topmodule name in chisel")
|
||||||
|
set(DIFFTEST_LIB "" CACHE STRING "Dynamic library file used as difftest reference")
|
||||||
|
|
||||||
|
# -- Ysyx tracker, configure
|
||||||
|
if(ENABLE_YSYX_GIT_TRACKER)
|
||||||
execute_process(
|
execute_process(
|
||||||
COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "configure(npc)"
|
COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "configure(npc)"
|
||||||
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/..
|
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/..
|
||||||
)
|
)
|
||||||
|
endif()
|
||||||
|
|
||||||
|
# -- Check dependencies
|
||||||
|
if(BUILD_SIM_TARGET)
|
||||||
|
find_package(verilator REQUIRED)
|
||||||
|
endif()
|
||||||
|
if(BUILD_SIM_NVBOARD_TARGET)
|
||||||
find_package(SDL2 REQUIRED)
|
find_package(SDL2 REQUIRED)
|
||||||
find_package(SDL2_image REQUIRED)
|
find_package(SDL2_image REQUIRED)
|
||||||
|
endif()
|
||||||
find_package(verilator REQUIRED)
|
find_package(CLI11 CONFIG REQUIRED)
|
||||||
|
|
||||||
find_library(NVBOARD_LIBRARY NAMES nvboard)
|
find_library(NVBOARD_LIBRARY NAMES nvboard)
|
||||||
find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h)
|
find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h)
|
||||||
|
|
||||||
set(TOPMODULES "Flow")
|
|
||||||
|
|
||||||
foreach(TOPMODULE IN LISTS TOPMODULES)
|
|
||||||
|
|
||||||
# FIXME: all scala source file are tracked here, cause all files to rebuild
|
# FIXME: all scala source file are tracked here, cause all files to rebuild
|
||||||
# after a source update.
|
# after a source update.
|
||||||
set(SCALA_CORE "${CMAKE_CURRENT_SOURCE_DIR}/core")
|
set(SCALA_CORE "${CMAKE_CURRENT_SOURCE_DIR}/core")
|
||||||
set(CHISEL_MODULE_CLASS "${CMAKE_PROJECT_NAME}.${TOPMODULE}")
|
set(CHISEL_MODULE_CLASS "${CMAKE_PROJECT_NAME}.${TOPMODULE}")
|
||||||
file(GLOB_RECURSE SCALA_CORE_SOURCES "${SCALA_CORE}/src/main/scala/*.scala")
|
|
||||||
file(GLOB_RECURSE SCALA_CORE_TEST_SOURCES "${SCALA_CORE}/src/test/scala/*.scala")
|
|
||||||
|
|
||||||
# Configure time verilog source generation for verilator
|
# Verilog files are generted in CHISEL_OUTPUT_TMP_DIR and copy to
|
||||||
execute_process(
|
# CHISEL_OUTPUT_DIR if content changes
|
||||||
COMMAND sbt "runMain circt.stage.ChiselMain --target-dir ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc --module ${CHISEL_MODULE_CLASS} --target verilog"
|
set(CHISEL_OUTPUT_DIR ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc)
|
||||||
WORKING_DIRECTORY ${SCALA_CORE}
|
set(CHISEL_OUTPUT_TMP_DIR ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc_tmp)
|
||||||
)
|
|
||||||
|
|
||||||
add_custom_command(
|
set(CHISEL_OUTPUT_VERILATOR_CONF ${CHISEL_OUTPUT_DIR}/conf.vlt)
|
||||||
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc/${TOPMODULE}.v
|
set(CHISEL_OUTPUT_TOPMODULE ${CHISEL_OUTPUT_DIR}/${TOPMODULE}.sv)
|
||||||
COMMAND sbt "runMain circt.stage.ChiselMain --target-dir ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc --module ${CHISEL_MODULE_CLASS} --target verilog"
|
set(CHISEL_EMIT_ARGS "--target-dir ${CHISEL_OUTPUT_TMP_DIR}")
|
||||||
WORKING_DIRECTORY ${SCALA_CORE}
|
|
||||||
DEPENDS ${SCALA_CORE_SOURCES}
|
|
||||||
)
|
|
||||||
|
|
||||||
add_custom_target(
|
|
||||||
ChiselBuild_${TOPMODULE}
|
|
||||||
DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc/${TOPMODULE}.v
|
|
||||||
)
|
|
||||||
|
|
||||||
# -- Build NVBoard executable
|
# -- Build NVBoard executable
|
||||||
|
if(BUILD_SIM_NVBOARD_TARGET)
|
||||||
add_custom_command(
|
add_subdirectory(csrc_nvboard)
|
||||||
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/auto_bind.cpp
|
endif()
|
||||||
COMMAND auto_pin_bind ${CMAKE_SOURCE_DIR}/constr/${TOPMODULE}.nxdc ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/auto_bind.cpp
|
|
||||||
DEPENDS ${CMAKE_SOURCE_DIR}/constr/${TOPMODULE}.nxdc
|
|
||||||
)
|
|
||||||
|
|
||||||
unset(SOURCES)
|
|
||||||
file(GLOB_RECURSE SOURCES csrc_nvboard/${TOPMODULE}/*.cpp)
|
|
||||||
add_executable(V${TOPMODULE}_nvboard ${SOURCES} ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/auto_bind.cpp)
|
|
||||||
|
|
||||||
verilate(V${TOPMODULE}_nvboard TRACE THREADS
|
|
||||||
TOP_MODULE ${TOPMODULE}
|
|
||||||
PREFIX V${TOPMODULE}
|
|
||||||
SOURCES ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc/${TOPMODULE}.v)
|
|
||||||
|
|
||||||
add_dependencies(V${TOPMODULE}_nvboard ChiselBuild_${TOPMODULE})
|
|
||||||
target_include_directories(V${TOPMODULE}_nvboard PRIVATE ${NVBOARD_INCLUDE_DIR} ${SDL2_INCLUDE_DIRS})
|
|
||||||
target_link_libraries(V${TOPMODULE}_nvboard PRIVATE ${NVBOARD_LIBRARY} SDL2::SDL2 SDL2_image::SDL2_image)
|
|
||||||
|
|
||||||
install(TARGETS V${TOPMODULE}_nvboard)
|
|
||||||
|
|
||||||
# -- Build Verilator executable and add to test
|
# -- Build Verilator executable and add to test
|
||||||
|
include_directories(include)
|
||||||
|
|
||||||
unset(SOURCES)
|
add_subdirectory(csrc)
|
||||||
file(GLOB_RECURSE SOURCES csrc/${TOPMODULE}/*.cpp)
|
|
||||||
add_executable(V${TOPMODULE} ${SOURCES})
|
|
||||||
|
|
||||||
verilate(V${TOPMODULE} TRACE COVERAGE THREADS
|
|
||||||
TOP_MODULE ${TOPMODULE}
|
|
||||||
PREFIX V${TOPMODULE}
|
|
||||||
SOURCES ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc/${TOPMODULE}.v)
|
|
||||||
|
|
||||||
add_dependencies(V${TOPMODULE} ChiselBuild_${TOPMODULE})
|
|
||||||
|
|
||||||
enable_testing()
|
|
||||||
add_test(NAME V${TOPMODULE} COMMAND V${TOPMODULE})
|
|
||||||
|
|
||||||
# -- Add build tracking
|
# -- Add build tracking
|
||||||
|
if(ENABLE_YSYX_GIT_TRACKER)
|
||||||
add_custom_command(
|
add_custom_command(
|
||||||
TARGET V${TOPMODULE}_nvboard PRE_BUILD
|
TARGET V${TOPMODULE}_nvboard PRE_BUILD
|
||||||
COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "build_${CMAKE_PROJECT_NAME}_V${TOPMODULE}_nvboard"
|
COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "build_${CMAKE_PROJECT_NAME}_V${TOPMODULE}_nvboard"
|
||||||
|
|
@ -97,5 +75,4 @@ foreach(TOPMODULE IN LISTS TOPMODULES)
|
||||||
COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "build_${CMAKE_PROJECT_NAME}_V${TOPMODULE}"
|
COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "build_${CMAKE_PROJECT_NAME}_V${TOPMODULE}"
|
||||||
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/..
|
WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/..
|
||||||
)
|
)
|
||||||
|
endif()
|
||||||
endforeach()
|
|
||||||
|
|
|
||||||
62
npc/cmake/ChiselBuild.cmake
Normal file
62
npc/cmake/ChiselBuild.cmake
Normal file
|
|
@ -0,0 +1,62 @@
|
||||||
|
# -- Add an always run target to generate verilog files with sbt/bloop,
|
||||||
|
# as we don't know if the result files will be different from cmake
|
||||||
|
# NOTE: Must reconfigure if we add new files in SCALA_CORE directory
|
||||||
|
file(GLOB_RECURSE SCALA_CORE_SOURCES "${SCALA_CORE}/src/main/scala/*.scala")
|
||||||
|
file(GLOB_RECURSE SCALA_CORE_RESOURCES "${SCALA_CORE}/src/main/resources/*")
|
||||||
|
set(CHISEL_DEPENDENCY ${SCALA_CORE_SOURCES} ${SCALA_CORE_RESOURCES} ${SCALA_CORE}/build.sbt)
|
||||||
|
|
||||||
|
if(BUILD_USE_BLOOP)
|
||||||
|
set(CHISEL_TARGET bloop_${TOPMODULE})
|
||||||
|
set(CHISEL_TEST_TARGET bloop_${TOPMODULE}_test)
|
||||||
|
# Export sbt build config to bloop
|
||||||
|
if(NOT EXISTS ${SCALA_CORE}/.bloop)
|
||||||
|
execute_process(
|
||||||
|
COMMAND sbt bloopInstall
|
||||||
|
WORKING_DIRECTORY ${SCALA_CORE}
|
||||||
|
)
|
||||||
|
endif()
|
||||||
|
string(REPLACE " " ";" CHISEL_EMIT_ARGS_LIST ${CHISEL_EMIT_ARGS})
|
||||||
|
list(TRANSFORM CHISEL_EMIT_ARGS_LIST PREPEND "--args;")
|
||||||
|
add_custom_command(
|
||||||
|
OUTPUT ${CHISEL_OUTPUT_TOPMODULE}
|
||||||
|
COMMAND bloop run root ${CHISEL_EMIT_ARGS_LIST}
|
||||||
|
COMMAND ${CMAKE_COMMAND} -E copy_directory_if_different ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR}
|
||||||
|
WORKING_DIRECTORY ${SCALA_CORE}
|
||||||
|
DEPENDS ${CHISEL_DEPENDENCY}
|
||||||
|
COMMAND_EXPAND_LISTS
|
||||||
|
COMMENT "Run bloop from CMake"
|
||||||
|
)
|
||||||
|
# add_test(
|
||||||
|
# NAME bloop_${TOPMODULE}_test
|
||||||
|
# COMMAND bloop test
|
||||||
|
# WORKING_DIRECTORY ${SCALA_CORE}
|
||||||
|
# )
|
||||||
|
else()
|
||||||
|
set(CHISEL_TARGET sbt_${TOPMODULE})
|
||||||
|
set(CHISEL_TEST_TARGET sbt_${TOPMODULE}_test)
|
||||||
|
add_custom_command(
|
||||||
|
OUTPUT ${CHISEL_OUTPUT_TOPMODULE}
|
||||||
|
COMMAND sbt "run ${CHISEL_EMIT_ARGS}"
|
||||||
|
COMMAND ${CMAKE_COMMAND} -E copy_directory_if_different ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR}
|
||||||
|
WORKING_DIRECTORY ${SCALA_CORE}
|
||||||
|
# DEPENDS ${CHISEL_DEPENDENCY} test.scala
|
||||||
|
VERBATIM
|
||||||
|
COMMENT "Run sbt from CMake"
|
||||||
|
)
|
||||||
|
add_test(
|
||||||
|
NAME sbt_${TOPMODULE}_test
|
||||||
|
COMMAND sbt test
|
||||||
|
WORKING_DIRECTORY ${SCALA_CORE}
|
||||||
|
)
|
||||||
|
endif()
|
||||||
|
|
||||||
|
if(NOT EXISTS ${CHISEL_OUTPUT_DIR})
|
||||||
|
# Probably cold build, generate verilog at configure time to produce top module file
|
||||||
|
execute_process(
|
||||||
|
COMMAND sbt "run ${CHISEL_EMIT_ARGS}"
|
||||||
|
WORKING_DIRECTORY ${SCALA_CORE}
|
||||||
|
)
|
||||||
|
execute_process(
|
||||||
|
COMMAND ${CMAKE_COMMAND} -E copy_directory ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR}
|
||||||
|
)
|
||||||
|
endif()
|
||||||
|
|
@ -3,6 +3,7 @@ ThisBuild / version := "0.1.0"
|
||||||
|
|
||||||
|
|
||||||
val chiselVersion = "6.2.0"
|
val chiselVersion = "6.2.0"
|
||||||
|
val circeVersion = "0.14.1"
|
||||||
|
|
||||||
lazy val root = (project in file("."))
|
lazy val root = (project in file("."))
|
||||||
.settings(
|
.settings(
|
||||||
|
|
@ -10,8 +11,13 @@ lazy val root = (project in file("."))
|
||||||
libraryDependencies ++= Seq(
|
libraryDependencies ++= Seq(
|
||||||
"org.chipsalliance" %% "chisel" % chiselVersion,
|
"org.chipsalliance" %% "chisel" % chiselVersion,
|
||||||
"edu.berkeley.cs" %% "chiseltest" % "6.0.0" % "test",
|
"edu.berkeley.cs" %% "chiseltest" % "6.0.0" % "test",
|
||||||
"com.chuusai" %% "shapeless" % "2.3.3"
|
"com.chuusai" %% "shapeless" % "2.3.3",
|
||||||
),
|
"com.github.scopt" %% "scopt" % "4.1.0",
|
||||||
|
) ++ Seq(
|
||||||
|
"io.circe" %% "circe-core",
|
||||||
|
"io.circe" %% "circe-generic",
|
||||||
|
"io.circe" %% "circe-parser"
|
||||||
|
).map(_ % circeVersion),
|
||||||
scalacOptions ++= Seq(
|
scalacOptions ++= Seq(
|
||||||
"-language:reflectiveCalls",
|
"-language:reflectiveCalls",
|
||||||
"-deprecation",
|
"-deprecation",
|
||||||
|
|
|
||||||
24
npc/core/src/main/resources/RamDpi.v
Normal file
24
npc/core/src/main/resources/RamDpi.v
Normal file
|
|
@ -0,0 +1,24 @@
|
||||||
|
import "DPI-C" function int pmem_read(input int addr);
|
||||||
|
import "DPI-C" function void pmem_write(input int waddr, input int wdata, input byte wmask);
|
||||||
|
|
||||||
|
module RamDpi (
|
||||||
|
input writeEnable,
|
||||||
|
input valid,
|
||||||
|
input [31:0] writeAddr,
|
||||||
|
input [31:0] writeData,
|
||||||
|
input [3:0] writeMask,
|
||||||
|
input reg [31:0] readAddr,
|
||||||
|
output reg [31:0] readData
|
||||||
|
);
|
||||||
|
always @(*) begin
|
||||||
|
if (valid) begin // 有读写请求时
|
||||||
|
readData = pmem_read(readAddr);
|
||||||
|
if (writeEnable) begin // 有写请求时
|
||||||
|
pmem_write(writeAddr, writeData, { 4'h0, writeMask });
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
readData = 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
@ -1,86 +0,0 @@
|
||||||
package flow.components
|
|
||||||
|
|
||||||
import chisel3._
|
|
||||||
import chisel3.util.log2Ceil
|
|
||||||
import chisel3.util.UIntToOH
|
|
||||||
import chisel3.util.MuxLookup
|
|
||||||
import shapeless.{ HNil, :: }
|
|
||||||
|
|
||||||
class RegControl extends Bundle {
|
|
||||||
object WriteSelect extends ChiselEnum {
|
|
||||||
val rAluOut, rMemOut = Value
|
|
||||||
}
|
|
||||||
|
|
||||||
val writeEnable = Input(Bool())
|
|
||||||
val writeSelect = Input(WriteSelect())
|
|
||||||
|
|
||||||
type CtrlTypes = Bool :: WriteSelect.Type :: HNil
|
|
||||||
def ctrlBindPorts: CtrlTypes = {
|
|
||||||
writeEnable :: writeSelect :: HNil
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
class RegFileData[T <: Data](size:Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
|
|
||||||
val write = new Bundle {
|
|
||||||
val addr = Input(UInt(size.W))
|
|
||||||
val data = Vec(numWritePorts, Input(tpe))
|
|
||||||
}
|
|
||||||
val read = Vec(numReadPorts, new Bundle {
|
|
||||||
val rs = Input(UInt(size.W))
|
|
||||||
val src = Output(tpe)
|
|
||||||
})
|
|
||||||
}
|
|
||||||
|
|
||||||
class RegFileInterface[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
|
|
||||||
val control = new RegControl
|
|
||||||
// val data = new RegFileData(size, tpe, numReadPorts, numWritePorts)
|
|
||||||
val in = new Bundle {
|
|
||||||
val writeAddr = Input(UInt(size.W))
|
|
||||||
val writeData = Input(Vec(numWritePorts, tpe))
|
|
||||||
val rs = Input(Vec(numReadPorts, UInt(size.W)))
|
|
||||||
}
|
|
||||||
val out = new Bundle {
|
|
||||||
val src = Output(Vec(numReadPorts, tpe))
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends Module {
|
|
||||||
require(numReadPorts >= 0)
|
|
||||||
val writePort = IO(new Bundle {
|
|
||||||
val enable = Input(Bool())
|
|
||||||
val addr = Input(UInt(log2Ceil(size).W))
|
|
||||||
val data = Input(tpe)
|
|
||||||
})
|
|
||||||
val readPorts = IO(Vec(numReadPorts, new Bundle {
|
|
||||||
val addr = Input(UInt(log2Ceil(size).W))
|
|
||||||
val data = Output(tpe)
|
|
||||||
}))
|
|
||||||
|
|
||||||
val regFile = RegInit(VecInit(Seq.fill(size)(0.U(tpe.getWidth.W))))
|
|
||||||
val writeAddrOH = UIntToOH(writePort.addr)
|
|
||||||
for ((reg, i) <- regFile.zipWithIndex.tail) {
|
|
||||||
reg := Mux(writeAddrOH(i) && writePort.enable, writePort.data, reg)
|
|
||||||
}
|
|
||||||
regFile(0) := 0.U
|
|
||||||
|
|
||||||
for (readPort <- readPorts) {
|
|
||||||
readPort.data := regFile(readPort.addr)
|
|
||||||
}
|
|
||||||
dontTouch(regFile)
|
|
||||||
}
|
|
||||||
|
|
||||||
object RegisterFile {
|
|
||||||
def apply[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int): RegFileInterface[T] = {
|
|
||||||
val core = Module(new RegisterFileCore(size, tpe, numReadPorts))
|
|
||||||
val _out = Wire(new RegFileInterface(size, tpe, numReadPorts, numWritePorts))
|
|
||||||
val clock = core.clock
|
|
||||||
for (i <- 0 until numReadPorts) {
|
|
||||||
core.readPorts(i).addr := _out.in.rs(i)
|
|
||||||
_out.out.src(i) := core.readPorts(i).data
|
|
||||||
}
|
|
||||||
core.writePort.addr := _out.in.writeAddr
|
|
||||||
core.writePort.data := _out.in.writeData(_out.control.writeSelect.asUInt)
|
|
||||||
core.writePort.enable := _out.control.writeEnable
|
|
||||||
_out
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
@ -9,7 +9,7 @@ class ALUControlInterface extends Bundle {
|
||||||
val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value
|
val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value
|
||||||
}
|
}
|
||||||
object SrcSelect extends ChiselEnum {
|
object SrcSelect extends ChiselEnum {
|
||||||
val aSrcRs1, aSrcImm = Value
|
val aSrcRs2, aSrcImm = Value
|
||||||
}
|
}
|
||||||
val op = Input(OpSelect())
|
val op = Input(OpSelect())
|
||||||
val src = Input(SrcSelect())
|
val src = Input(SrcSelect())
|
||||||
24
npc/core/src/main/scala/components/Mem.scala
Normal file
24
npc/core/src/main/scala/components/Mem.scala
Normal file
|
|
@ -0,0 +1,24 @@
|
||||||
|
package flow.components
|
||||||
|
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util.HasBlackBoxPath
|
||||||
|
import chisel3.util.HasBlackBoxResource
|
||||||
|
import chisel3.util.log2Ceil
|
||||||
|
import chisel3.experimental.noPrefix
|
||||||
|
import scala.collection.SeqMap
|
||||||
|
import javax.swing.plaf.synth.SynthRadioButtonMenuItemUI
|
||||||
|
|
||||||
|
class RamInterface[T <: Data](tpe: T, addrWidth: Int) extends Bundle {
|
||||||
|
val valid = Input(Bool())
|
||||||
|
val writeEnable = Input(Bool())
|
||||||
|
val writeAddr = Input(UInt(addrWidth.W))
|
||||||
|
val writeData = Input(tpe)
|
||||||
|
val writeMask = Input(UInt((addrWidth / 8).W))
|
||||||
|
val readAddr = Input(UInt(addrWidth.W))
|
||||||
|
val readData = Output(tpe)
|
||||||
|
}
|
||||||
|
|
||||||
|
class RamDpi extends BlackBox with HasBlackBoxResource {
|
||||||
|
val io = IO(new RamInterface(UInt(32.W), 32))
|
||||||
|
addResource("/RamDpi.v")
|
||||||
|
}
|
||||||
52
npc/core/src/main/scala/components/RegisterFile.scala
Normal file
52
npc/core/src/main/scala/components/RegisterFile.scala
Normal file
|
|
@ -0,0 +1,52 @@
|
||||||
|
package flow.components
|
||||||
|
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util.log2Ceil
|
||||||
|
import chisel3.util.UIntToOH
|
||||||
|
import chisel3.util.MuxLookup
|
||||||
|
import chisel3.experimental.Trace._
|
||||||
|
import shapeless.{ HNil, :: }
|
||||||
|
|
||||||
|
class RegControl extends Bundle {
|
||||||
|
object WriteSelect extends ChiselEnum {
|
||||||
|
val rAluOut, rMemOut = Value
|
||||||
|
}
|
||||||
|
|
||||||
|
val writeEnable = Input(Bool())
|
||||||
|
val writeSelect = Input(WriteSelect())
|
||||||
|
|
||||||
|
type CtrlTypes = Bool :: WriteSelect.Type :: HNil
|
||||||
|
def ctrlBindPorts: CtrlTypes = {
|
||||||
|
writeEnable :: writeSelect :: HNil
|
||||||
|
}
|
||||||
|
traceName(writeEnable)
|
||||||
|
}
|
||||||
|
|
||||||
|
class RegisterFile[T <: Data](tpe: T, regCount: Int, numReadPorts: Int) extends Module {
|
||||||
|
require(numReadPorts >= 0)
|
||||||
|
val control = IO(new RegControl)
|
||||||
|
val dataAddrWidth = log2Ceil(regCount).W
|
||||||
|
val in = IO(new Bundle {
|
||||||
|
val writeAddr = Input(UInt(dataAddrWidth))
|
||||||
|
val writeData = Input(Vec(control.WriteSelect.all.length, tpe))
|
||||||
|
val rs = Input(Vec(numReadPorts, UInt(dataAddrWidth)))
|
||||||
|
})
|
||||||
|
val out = IO(new Bundle {
|
||||||
|
val src = Output(Vec(numReadPorts, tpe))
|
||||||
|
})
|
||||||
|
|
||||||
|
val regResetValue = 0.U(tpe.getWidth.W)
|
||||||
|
val regFile = RegInit(VecInit(Seq.fill(regCount)(regResetValue)))
|
||||||
|
val writeAddrOH = UIntToOH(in.writeAddr)
|
||||||
|
|
||||||
|
for ((reg, i) <- regFile.zipWithIndex.tail) {
|
||||||
|
reg := Mux(writeAddrOH(i.U(log2Ceil(regCount).W)) && control.writeEnable, in.writeData(control.writeSelect.asUInt), reg)
|
||||||
|
}
|
||||||
|
regFile(0) := 0.U
|
||||||
|
|
||||||
|
for (port <- 0 until numReadPorts) {
|
||||||
|
out.src(port) := regFile(in.rs(port).asUInt)
|
||||||
|
}
|
||||||
|
traceName(regFile)
|
||||||
|
dontTouch(regFile)
|
||||||
|
}
|
||||||
47
npc/core/src/main/scala/top/ArgParse.scala
Normal file
47
npc/core/src/main/scala/top/ArgParse.scala
Normal file
|
|
@ -0,0 +1,47 @@
|
||||||
|
package flow
|
||||||
|
|
||||||
|
import scopt.{ OParser, DefaultOEffectSetup }
|
||||||
|
import java.io.File
|
||||||
|
|
||||||
|
case class CliOptions(
|
||||||
|
targetDir: File = new File("."),
|
||||||
|
configFile: Option[File] = None,
|
||||||
|
argsFile: Option[File] = None,
|
||||||
|
verilatorConfigFileOut: File = new File("conf.vlt"),
|
||||||
|
) {
|
||||||
|
val builder = OParser.builder[CliOptions]
|
||||||
|
val parser = {
|
||||||
|
import builder._
|
||||||
|
OParser.sequence(
|
||||||
|
programName("flow"),
|
||||||
|
help("help"),
|
||||||
|
opt[Option[File]]('c', "config")
|
||||||
|
.action((x, c) => c.copy(configFile = x))
|
||||||
|
.text("JSON Configuration file for generation"),
|
||||||
|
opt[Option[File]]("args-file")
|
||||||
|
.action((x, c) => c.copy(argsFile = x))
|
||||||
|
.text("Passing file content as args when emit"),
|
||||||
|
opt[File]('o', "target-dir")
|
||||||
|
.action((x, c) => c.copy(targetDir = x))
|
||||||
|
.text("Output files relative to this path"),
|
||||||
|
opt[File]("out-verilator-conf")
|
||||||
|
.action((x, c) => c.copy(verilatorConfigFileOut = x))
|
||||||
|
.text("Options needed when simulating with verilator")
|
||||||
|
)
|
||||||
|
}
|
||||||
|
|
||||||
|
def parse(args: Array[String]): CliOptions = {
|
||||||
|
OParser.runParser(parser, args, CliOptions()) match {
|
||||||
|
case (result, effects) =>
|
||||||
|
OParser.runEffects(effects, new DefaultOEffectSetup {
|
||||||
|
// ignore terminate
|
||||||
|
override def terminate(exitState: Either[String, Unit]): Unit = ()
|
||||||
|
})
|
||||||
|
|
||||||
|
result match {
|
||||||
|
case Some(cliOptions: CliOptions) => { return cliOptions }
|
||||||
|
case _ => { throw new IllegalArgumentException("Wrong command line argument") }
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
16
npc/core/src/main/scala/top/Config.scala
Normal file
16
npc/core/src/main/scala/top/Config.scala
Normal file
|
|
@ -0,0 +1,16 @@
|
||||||
|
package flow
|
||||||
|
|
||||||
|
import io.circe.generic.JsonCodec
|
||||||
|
|
||||||
|
// Which group of signals to trace
|
||||||
|
@JsonCodec case class TraceConfig (
|
||||||
|
enable: Boolean = false,
|
||||||
|
registers: Array[Int] = Array(),
|
||||||
|
mem: Array[(Int, Int)] = Array(),
|
||||||
|
)
|
||||||
|
|
||||||
|
@JsonCodec case class Config(
|
||||||
|
// Whether to enable Difftest
|
||||||
|
enableDifftest: Boolean = true,
|
||||||
|
traceConfig: TraceConfig = TraceConfig(),
|
||||||
|
)
|
||||||
|
|
@ -5,16 +5,17 @@ import chisel3._
|
||||||
import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
|
import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
|
||||||
import chisel3.util.{SRAM}
|
import chisel3.util.{SRAM}
|
||||||
import chisel3.util.experimental.decode.{decoder, TruthTable}
|
import chisel3.util.experimental.decode.{decoder, TruthTable}
|
||||||
import chisel3.stage.ChiselOption
|
|
||||||
import chisel3.util.log2Ceil
|
import chisel3.util.log2Ceil
|
||||||
import chisel3.util.BitPat
|
import chisel3.util.BitPat
|
||||||
import chisel3.util.Enum
|
import chisel3.util.Enum
|
||||||
import chisel3.experimental.prefix
|
import chisel3.experimental.Trace._
|
||||||
import shapeless.{HNil, ::}
|
import shapeless.{HNil, ::}
|
||||||
import shapeless.HList
|
import shapeless.HList
|
||||||
import shapeless.ops.coproduct.Prepend
|
import shapeless.ops.coproduct.Prepend
|
||||||
import chisel3.util.{ BinaryMemoryFile, HexMemoryFile }
|
import chisel3.util.{ BinaryMemoryFile, HexMemoryFile }
|
||||||
|
|
||||||
|
import chisel3.experimental.Trace
|
||||||
|
|
||||||
object RV32Inst {
|
object RV32Inst {
|
||||||
private val bp = BitPat
|
private val bp = BitPat
|
||||||
val addi = this.bp("b???????_?????_?????_000_?????_00100_11")
|
val addi = this.bp("b???????_?????_?????_000_?????_00100_11")
|
||||||
|
|
@ -73,27 +74,20 @@ class Control(width: Int) extends Module {
|
||||||
})
|
})
|
||||||
}
|
}
|
||||||
|
|
||||||
import flow.components.{RegisterFile, RegFileInterface, ProgramCounter, ALU}
|
import flow.components.{RegisterFile, ProgramCounter, ALU, RamDpi}
|
||||||
import chisel3.util.experimental.loadMemoryFromFileInline
|
import chisel3.util.experimental.loadMemoryFromFileInline
|
||||||
class Flow extends Module {
|
class Flow extends Module {
|
||||||
val dataType = UInt(32.W)
|
val dataType = UInt(32.W)
|
||||||
|
val ram = Module(new RamDpi)
|
||||||
val ram = SRAM(
|
|
||||||
size = 1024,
|
|
||||||
tpe = dataType,
|
|
||||||
numReadPorts = 2,
|
|
||||||
numWritePorts = 1,
|
|
||||||
numReadwritePorts = 0,
|
|
||||||
memoryFile = HexMemoryFile("./resource/addi.txt")
|
|
||||||
)
|
|
||||||
val control = Module(new Control(32))
|
val control = Module(new Control(32))
|
||||||
val reg = RegisterFile(32, dataType, 2, 2)
|
val reg = Module(new RegisterFile(dataType, 32, 2))
|
||||||
val pc = Module(new ProgramCounter(dataType))
|
val pc = Module(new ProgramCounter(dataType))
|
||||||
val alu = Module(new ALU(dataType))
|
val alu = Module(new ALU(dataType))
|
||||||
|
|
||||||
ram.readPorts(0).enable := true.B
|
ram.io.readAddr := pc.out
|
||||||
ram.readPorts(0).address := pc.out - 0x80000000L.U
|
val inst = ram.io.readData
|
||||||
val inst = ram.readPorts(0).data
|
|
||||||
|
dontTouch(reg.control.writeEnable)
|
||||||
|
|
||||||
import control.pc.SrcSelect._
|
import control.pc.SrcSelect._
|
||||||
|
|
||||||
|
|
@ -107,23 +101,26 @@ class Flow extends Module {
|
||||||
|
|
||||||
import control.reg.WriteSelect._
|
import control.reg.WriteSelect._
|
||||||
reg.in.writeData(rAluOut.litValue.toInt) := alu.out.result
|
reg.in.writeData(rAluOut.litValue.toInt) := alu.out.result
|
||||||
|
|
||||||
// TODO: Read address in load command goes here
|
// TODO: Read address in load command goes here
|
||||||
ram.readPorts(1).enable := false.B
|
reg.in.writeData(rMemOut.litValue.toInt) := DontCare
|
||||||
ram.readPorts(1).address := 0.U
|
|
||||||
reg.in.writeData(rMemOut.litValue.toInt) := ram.readPorts(1).data
|
|
||||||
reg.in.writeAddr := inst(11, 7)
|
reg.in.writeAddr := inst(11, 7)
|
||||||
reg.in.rs(0) := inst(19, 15)
|
reg.in.rs(0) := inst(19, 15) // rs1
|
||||||
reg.in.rs(1) := inst(24, 20)
|
reg.in.rs(1) := inst(24, 20) // rs2
|
||||||
|
|
||||||
// TODO: Memory write goes here
|
// TODO: Memory write goes here
|
||||||
ram.writePorts(0).address := 1.U
|
ram.io.writeAddr := DontCare
|
||||||
ram.writePorts(0).data := 1.U
|
ram.io.writeData := DontCare
|
||||||
ram.writePorts(0).enable := false.B
|
ram.io.writeMask := DontCare
|
||||||
|
ram.io.writeEnable := false.B
|
||||||
|
ram.io.valid := true.B
|
||||||
|
|
||||||
import control.alu.SrcSelect._
|
import control.alu.SrcSelect._
|
||||||
alu.in.a(aSrcRs1.litValue.toInt) := reg.out.src(0)
|
alu.in.a(aSrcRs2.litValue.toInt) := reg.out.src(1)
|
||||||
alu.in.a(aSrcImm.litValue.toInt) := inst(31, 20)
|
alu.in.a(aSrcImm.litValue.toInt) := inst(31, 20)
|
||||||
alu.in.b := reg.out.src(1)
|
alu.in.b := reg.out.src(0)
|
||||||
|
|
||||||
|
Trace.traceName(pc.out);
|
||||||
dontTouch(control.out)
|
dontTouch(control.out)
|
||||||
}
|
}
|
||||||
72
npc/core/src/main/scala/top/Main.scala
Normal file
72
npc/core/src/main/scala/top/Main.scala
Normal file
|
|
@ -0,0 +1,72 @@
|
||||||
|
package flow
|
||||||
|
|
||||||
|
import flow._
|
||||||
|
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.experimental.Trace._
|
||||||
|
import chisel3.stage.{ChiselGeneratorAnnotation, DesignAnnotation}
|
||||||
|
import chisel3.util.experimental.InlineInstance
|
||||||
|
import circt.stage.ChiselStage
|
||||||
|
import firrtl.AnnotationSeq
|
||||||
|
import firrtl.annotations.TargetToken.{Instance, OfModule, Ref}
|
||||||
|
import java.io.PrintWriter
|
||||||
|
import scala.io.Source
|
||||||
|
import java.io.File
|
||||||
|
|
||||||
|
|
||||||
|
// TODO: Generate verilator config file
|
||||||
|
|
||||||
|
object VerilogMain extends App {
|
||||||
|
val opt = CliOptions().parse(args)
|
||||||
|
val topName = "Flow"
|
||||||
|
|
||||||
|
val config: Config = opt.configFile match {
|
||||||
|
case Some(f) => {
|
||||||
|
val source = Source.fromFile(f)
|
||||||
|
val jsonString = source.mkString
|
||||||
|
source.close()
|
||||||
|
io.circe.parser.decode[Config](jsonString) match {
|
||||||
|
case Right(x) => x
|
||||||
|
case Left(e) => throw e
|
||||||
|
}
|
||||||
|
}
|
||||||
|
case None => Config(traceConfig = TraceConfig(enable = true))
|
||||||
|
}
|
||||||
|
|
||||||
|
val annos = (new ChiselStage).execute(
|
||||||
|
Array("--target-dir", opt.targetDir.toString, "--target", "systemverilog", "--split-verilog"),
|
||||||
|
Seq(
|
||||||
|
|
||||||
|
) ++ (if(config.traceConfig.enable) Seq(ChiselGeneratorAnnotation(() => new Flow)) else Seq())
|
||||||
|
)
|
||||||
|
|
||||||
|
if(config.traceConfig.enable) {
|
||||||
|
val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[Flow]
|
||||||
|
|
||||||
|
val verilatorConfigSeq = finalTargetMap(annos)
|
||||||
|
.values
|
||||||
|
.flatten
|
||||||
|
.map(ct =>
|
||||||
|
s"""public_flat_rd -module "${
|
||||||
|
ct.tokens.collectFirst { case OfModule(m) => m }.get
|
||||||
|
}" -var "${ct.tokens.collectFirst { case Ref(r) => r }.get}"""")
|
||||||
|
finalTargetMap(annos)
|
||||||
|
.values
|
||||||
|
.flatten
|
||||||
|
.foreach(
|
||||||
|
ct => println(s"""TOP.${ct.circuit}.${ct.path.map { case (Instance(i), _) => i }.mkString(".")}.${ct.tokens.collectFirst {
|
||||||
|
case Ref(r) => r
|
||||||
|
}.get}""")
|
||||||
|
)
|
||||||
|
|
||||||
|
val verilatorConfigWriter = new PrintWriter(new File(opt.targetDir, opt.verilatorConfigFileOut.toString()))
|
||||||
|
verilatorConfigWriter.write("`verilator_config\n")
|
||||||
|
try {
|
||||||
|
for(ct <- verilatorConfigSeq) {
|
||||||
|
verilatorConfigWriter.println(ct)
|
||||||
|
}
|
||||||
|
} finally {
|
||||||
|
verilatorConfigWriter.close()
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
11
npc/core/src/main/scala/utils/DPI.scala
Normal file
11
npc/core/src/main/scala/utils/DPI.scala
Normal file
|
|
@ -0,0 +1,11 @@
|
||||||
|
package flow.utils
|
||||||
|
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util.HasBlackBoxResource
|
||||||
|
|
||||||
|
// class DiffTester extends BlackBox with HasBlackBoxResource {
|
||||||
|
// val io = IO(new Bundle {
|
||||||
|
// val regs =
|
||||||
|
// })
|
||||||
|
// addResource("difftest.v");
|
||||||
|
// }
|
||||||
1
npc/csrc/CMakeLists.txt
Normal file
1
npc/csrc/CMakeLists.txt
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
add_subdirectory(${TOPMODULE})
|
||||||
17
npc/csrc/Flow/CMakeLists.txt
Normal file
17
npc/csrc/Flow/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,17 @@
|
||||||
|
include(ChiselBuild)
|
||||||
|
add_executable(V${TOPMODULE} config.cpp main.cpp)
|
||||||
|
|
||||||
|
verilate(V${TOPMODULE} TRACE COVERAGE THREADS
|
||||||
|
TOP_MODULE ${TOPMODULE}
|
||||||
|
PREFIX V${TOPMODULE}
|
||||||
|
SOURCES ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF}
|
||||||
|
INCLUDE_DIRS ${CHISEL_OUTPUT_DIR}
|
||||||
|
VERILATOR_ARGS
|
||||||
|
"--vpi" # Enable VPI
|
||||||
|
)
|
||||||
|
|
||||||
|
add_test(
|
||||||
|
NAME V${TOPMODULE}
|
||||||
|
COMMAND V${TOPMODULE}
|
||||||
|
--no-bin -m ${PROJECT_SOURCE_DIR}/resource/addi.txt
|
||||||
|
--diff-lib ${DIFFTEST_LIB})
|
||||||
110
npc/csrc/Flow/components.hpp
Normal file
110
npc/csrc/Flow/components.hpp
Normal file
|
|
@ -0,0 +1,110 @@
|
||||||
|
|
||||||
|
#ifndef _NPC_COMPONENTS_H_
|
||||||
|
#define _NPC_COMPONENTS_H_
|
||||||
|
#include "vpi_user.h"
|
||||||
|
#include <array>
|
||||||
|
#include <cstdlib>
|
||||||
|
#include <filesystem>
|
||||||
|
#include <fstream>
|
||||||
|
#include <iostream>
|
||||||
|
#include <verilated_vpi.h>
|
||||||
|
|
||||||
|
template <typename T, std::size_t nr> class _RegistersBase {
|
||||||
|
std::array<T, nr> regs;
|
||||||
|
T pc;
|
||||||
|
virtual T fetch_pc();
|
||||||
|
virtual T fetch_reg(std::size_t id);
|
||||||
|
|
||||||
|
public:
|
||||||
|
T operator[](size_t id) { return fetch_reg(id); }
|
||||||
|
T get_pc() { return fetch_pc(); }
|
||||||
|
void update() {
|
||||||
|
for (int i = 0; i < regs.size(); i++) {
|
||||||
|
regs[i] = fetch_reg(i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
template <typename T, std::size_t nr>
|
||||||
|
class _RegistersVPI : public _RegistersBase<T, nr> {
|
||||||
|
std::array<vpiHandle, nr> reg_handles;
|
||||||
|
vpiHandle pc_handle;
|
||||||
|
T vpi_get(vpiHandle vh) {
|
||||||
|
s_vpi_value v;
|
||||||
|
v.format = vpiIntVal;
|
||||||
|
vpi_get_value(vh, &v);
|
||||||
|
return v.value.integer;
|
||||||
|
}
|
||||||
|
T fetch_pc(void) { return vpi_get(pc_handle); }
|
||||||
|
T fetch_reg(std::size_t id) { return vpi_get(reg_handles[id]); }
|
||||||
|
|
||||||
|
public:
|
||||||
|
_RegistersVPI<T, nr>(const std::string regs_prefix,
|
||||||
|
const std::string pcname) {
|
||||||
|
for (int i = 0; i < nr; i++) {
|
||||||
|
std::string regname = regs_prefix + std::to_string(i);
|
||||||
|
vpiHandle vh = vpi_handle_by_name((PLI_BYTE8 *)regname.c_str(), nullptr);
|
||||||
|
if (vh == nullptr) {
|
||||||
|
std::cerr << "vpiHandle " << regname.c_str() << " not found"
|
||||||
|
<< std::endl;
|
||||||
|
exit(EXIT_FAILURE);
|
||||||
|
}
|
||||||
|
reg_handles[i] = vh;
|
||||||
|
}
|
||||||
|
pc_handle = vpi_handle_by_name((PLI_BYTE8 *)pcname.c_str(), nullptr);
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
template <typename T, std::size_t n> class Memory {
|
||||||
|
std::size_t addr_to_index(std::size_t addr) {
|
||||||
|
if (addr < 0x80000000) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
// Linear mapping
|
||||||
|
return (addr >> 2) - 0x20000000;
|
||||||
|
}
|
||||||
|
uint32_t expand_bits(uint8_t bits) {
|
||||||
|
uint32_t x = bits;
|
||||||
|
x = (x | (x << 7) | (x << 14) | (x << 21)) & 0x01010101;
|
||||||
|
x = x * 0xFF;
|
||||||
|
// printf("expand: %hhx->%x\n", bits, x);
|
||||||
|
return x;
|
||||||
|
}
|
||||||
|
|
||||||
|
public:
|
||||||
|
std::array<T, n> mem;
|
||||||
|
Memory(std::filesystem::path filepath, bool is_binary = true) {
|
||||||
|
assert(std::filesystem::exists(filepath));
|
||||||
|
if (is_binary) {
|
||||||
|
std::ifstream file(filepath, std::ios::binary);
|
||||||
|
char *pmem = reinterpret_cast<char *>(mem.data());
|
||||||
|
file.read(pmem, mem.size() * sizeof(mem[0]));
|
||||||
|
} else {
|
||||||
|
std::string line;
|
||||||
|
std::ifstream file(filepath);
|
||||||
|
int i = 0;
|
||||||
|
while (std::getline(file, line)) {
|
||||||
|
mem[i++] = std::stoul(line, 0, 16);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
const T &operator[](std::size_t addr) { return this->read(addr); }
|
||||||
|
/**
|
||||||
|
* Always reads and returns 4 bytes from the address raddr & ~0x3u.
|
||||||
|
*/
|
||||||
|
T read(int raddr) {
|
||||||
|
// printf("raddr: 0x%x\n", raddr);
|
||||||
|
return mem[addr_to_index((uint32_t)raddr)];
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* Always writes to the 4 bytes at the address `waddr` & ~0x3u.
|
||||||
|
* Each bit in `wmask` represents a mask for one byte in wdata.
|
||||||
|
* For example, wmask = 0x3 means only the lowest 2 bytes are written,
|
||||||
|
* and the other bytes in memory remain unchanged.
|
||||||
|
*/
|
||||||
|
void write(int waddr, T wdata, char wmask) {
|
||||||
|
// printf("waddr: 0x%x\n", waddr);
|
||||||
|
mem[addr_to_index((uint32_t)waddr)] = expand_bits(wmask) & wdata;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
30
npc/csrc/Flow/config.cpp
Normal file
30
npc/csrc/Flow/config.cpp
Normal file
|
|
@ -0,0 +1,30 @@
|
||||||
|
#include "config.hpp"
|
||||||
|
|
||||||
|
void Config::cli_parse(int argc, char **argv) {
|
||||||
|
CLI::App app;
|
||||||
|
app.add_option("-m,--memory", memory_file, "Content of memory")
|
||||||
|
->required()
|
||||||
|
->check(CLI::ExistingFile);
|
||||||
|
app.add_flag("!--no-bin", memory_file_binary,
|
||||||
|
"Memory file is in text format");
|
||||||
|
app.add_flag("--trace", do_trace, "Enable tracing");
|
||||||
|
app.add_option("--wav", wavefile, "output .vcd file path")
|
||||||
|
->check([=](const std::string &) {
|
||||||
|
if (!do_trace)
|
||||||
|
throw CLI::ValidationError(
|
||||||
|
"dependency", "You must turn on trace before specify wave file");
|
||||||
|
return std::string();
|
||||||
|
});
|
||||||
|
app.add_option("-t", max_sim_time, "Max simulation timestep");
|
||||||
|
app.add_option("--diff-lib", lib_ref,
|
||||||
|
"Dynamic library file of difftest reference")
|
||||||
|
->check(CLI::ExistingFile);
|
||||||
|
|
||||||
|
try {
|
||||||
|
app.parse(argc, argv);
|
||||||
|
} catch (const CLI::ParseError &e) {
|
||||||
|
exit((app).exit(e));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
Config config;
|
||||||
20
npc/csrc/Flow/config.hpp
Normal file
20
npc/csrc/Flow/config.hpp
Normal file
|
|
@ -0,0 +1,20 @@
|
||||||
|
#ifndef _NPC_CONFIG_H_
|
||||||
|
#define _NPC_CONFIG_H_
|
||||||
|
#include <CLI/App.hpp>
|
||||||
|
#include <CLI/CLI.hpp>
|
||||||
|
#include <CLI/Validators.hpp>
|
||||||
|
#include <filesystem>
|
||||||
|
|
||||||
|
struct Config {
|
||||||
|
std::filesystem::path memory_file;
|
||||||
|
uint64_t max_sim_time = 1000;
|
||||||
|
bool memory_file_binary = {true};
|
||||||
|
bool do_trace{false};
|
||||||
|
std::filesystem::path wavefile;
|
||||||
|
std::filesystem::path lib_ref;
|
||||||
|
void cli_parse(int argc, char **argv);
|
||||||
|
};
|
||||||
|
|
||||||
|
extern Config config;
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -1,43 +1,85 @@
|
||||||
#include <cstdlib>
|
#include "components.hpp"
|
||||||
#include <cassert>
|
#include "config.hpp"
|
||||||
#include <cstdlib>
|
#include "vl_wrapper.hpp"
|
||||||
#include <verilated.h>
|
#include "vpi_user.h"
|
||||||
#include <verilated_vcd_c.h>
|
|
||||||
#include <VFlow.h>
|
#include <VFlow.h>
|
||||||
#define MAX_SIM_TIME 100
|
#include <cstdint>
|
||||||
#define VERILATOR_TRACE
|
#include <difftest.hpp>
|
||||||
|
|
||||||
|
using VlModule = VlModuleInterfaceCommon<VFlow>;
|
||||||
|
using Registers = _RegistersVPI<uint32_t, 32>;
|
||||||
|
|
||||||
|
extern "C" {
|
||||||
|
void *pmem_get() {
|
||||||
|
static auto pmem = new Memory<int, 128 * 1024>(config.memory_file,
|
||||||
|
config.memory_file_binary);
|
||||||
|
return pmem;
|
||||||
|
}
|
||||||
|
|
||||||
|
int pmem_read(int raddr) {
|
||||||
|
void *pmem = pmem_get();
|
||||||
|
auto mem = static_cast<Memory<int, 128 * 1024> *>(pmem);
|
||||||
|
// TODO: Do memory difftest at memory read and write to diagnose at a finer
|
||||||
|
// granularity
|
||||||
|
return mem->read(raddr);
|
||||||
|
}
|
||||||
|
|
||||||
|
void pmem_write(int waddr, int wdata, char wmask) {
|
||||||
|
void *pmem = pmem_get();
|
||||||
|
auto mem = static_cast<Memory<int, 128 * 1024> *>(pmem);
|
||||||
|
return mem->write((std::size_t)waddr, wdata, wmask);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
VlModule *top;
|
||||||
|
Registers *regs;
|
||||||
|
using CPUState = CPUStateBase<uint32_t, 32>;
|
||||||
|
vpiHandle pc = nullptr;
|
||||||
|
void difftest_memcpy(paddr_t, void *, size_t, bool){};
|
||||||
|
|
||||||
|
void difftest_regcpy(void *p, bool direction) {
|
||||||
|
|
||||||
|
if (direction == DIFFTEST_FROM_REF) {
|
||||||
|
((CPUState *)p)->pc = regs->get_pc();
|
||||||
|
for (int i = 0; i < 32; i++) {
|
||||||
|
((CPUState *)p)->reg[i] = (*regs)[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void difftest_exec(uint64_t n) {
|
||||||
|
while (n--) {
|
||||||
|
for (int i = 0; i < 2; i++) {
|
||||||
|
if (top->is_posedge()) {
|
||||||
|
// Posedge
|
||||||
|
regs->update();
|
||||||
|
}
|
||||||
|
top->eval();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
void difftest_init(int port) {
|
||||||
|
// top = std::make_unique<VlModule>(config.do_trace, config.wavefile);
|
||||||
|
top = new VlModule{config.do_trace, config.wavefile};
|
||||||
|
regs = new Registers("TOP.Flow.reg_0.regFile_", "TOP.Flow.pc.out");
|
||||||
|
top->reset_eval(10);
|
||||||
|
}
|
||||||
|
|
||||||
int main(int argc, char **argv, char **env) {
|
int main(int argc, char **argv, char **env) {
|
||||||
int sim_time = 0;
|
config.cli_parse(argc, argv);
|
||||||
Verilated::commandArgs(argc, argv);
|
|
||||||
|
|
||||||
VFlow *top = new VFlow;
|
/* -- Difftest -- */
|
||||||
|
std::filesystem::path ref{config.lib_ref};
|
||||||
|
DifftestInterface dut_interface = DifftestInterface{
|
||||||
|
&difftest_memcpy, &difftest_regcpy, &difftest_exec, &difftest_init};
|
||||||
|
DifftestInterface ref_interface = DifftestInterface{ref};
|
||||||
|
|
||||||
Verilated::traceEverOn(true);
|
Difftest<CPUStateBase<uint32_t, 32>> diff{dut_interface, ref_interface,
|
||||||
VerilatedVcdC *m_trace = new VerilatedVcdC;
|
pmem_get(), 128};
|
||||||
#ifdef VERILATOR_TRACE
|
int t = 8;
|
||||||
top->trace(m_trace, 5);
|
while (t--) {
|
||||||
m_trace->open("waveform.vcd");
|
diff.step(1);
|
||||||
#endif
|
|
||||||
for (sim_time = 0; sim_time < 10; sim_time++) {
|
|
||||||
top->eval();
|
|
||||||
top->clock = !top->clock;
|
|
||||||
top->reset = 1;
|
|
||||||
#ifdef VERILATOR_TRACE
|
|
||||||
m_trace->dump(sim_time);
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
top->reset = 0;
|
|
||||||
for (sim_time = 10; sim_time < MAX_SIM_TIME; sim_time++) {
|
return 0;
|
||||||
top->eval();
|
|
||||||
top->clock = !top->clock;
|
|
||||||
#ifdef VERILATOR_TRACE
|
|
||||||
m_trace->dump(sim_time);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#ifdef VERILATOR_TRACE
|
|
||||||
m_trace->close();
|
|
||||||
#endif
|
|
||||||
delete top;
|
|
||||||
exit(EXIT_SUCCESS);
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
65
npc/csrc/Flow/vl_wrapper.hpp
Normal file
65
npc/csrc/Flow/vl_wrapper.hpp
Normal file
|
|
@ -0,0 +1,65 @@
|
||||||
|
#ifndef _NPC_TRACER_H_
|
||||||
|
#define _NPC_TRACER_H_
|
||||||
|
#include <filesystem>
|
||||||
|
#include <verilated_vcd_c.h>
|
||||||
|
|
||||||
|
template <class T> class Tracer {
|
||||||
|
std::shared_ptr<T> top;
|
||||||
|
std::unique_ptr<VerilatedVcdC> m_trace;
|
||||||
|
uint64_t cycle = 0;
|
||||||
|
|
||||||
|
public:
|
||||||
|
Tracer(T *top, std::filesystem::path wavefile) {
|
||||||
|
top = top;
|
||||||
|
Verilated::traceEverOn(true);
|
||||||
|
m_trace = std::make_unique<VerilatedVcdC>();
|
||||||
|
top->trace(m_trace.get(), 5);
|
||||||
|
m_trace->open(wavefile.c_str());
|
||||||
|
}
|
||||||
|
~Tracer() { m_trace->close(); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Dump signals to waveform file. Must be called once after every top->eval()
|
||||||
|
* call.
|
||||||
|
*/
|
||||||
|
void update() { m_trace->dump(cycle++); }
|
||||||
|
};
|
||||||
|
|
||||||
|
template <typename T> class VlModuleInterfaceCommon : public T {
|
||||||
|
uint64_t sim_time = 0;
|
||||||
|
uint64_t posedge_cnt = 0;
|
||||||
|
std::unique_ptr<Tracer<T>> tracer;
|
||||||
|
|
||||||
|
public:
|
||||||
|
VlModuleInterfaceCommon<T>(bool do_trace,
|
||||||
|
std::filesystem::path wavefile = "waveform.vcd") {
|
||||||
|
if (do_trace)
|
||||||
|
tracer = std::make_unique<Tracer<T>>(this, wavefile);
|
||||||
|
}
|
||||||
|
void eval() {
|
||||||
|
if (this->is_posedge()) {
|
||||||
|
posedge_cnt++;
|
||||||
|
}
|
||||||
|
T::clock = !T::clock;
|
||||||
|
sim_time++;
|
||||||
|
T::eval();
|
||||||
|
if (tracer)
|
||||||
|
tracer->update();
|
||||||
|
}
|
||||||
|
void eval(int n) {
|
||||||
|
for (int i = 0; i < n; i++) {
|
||||||
|
this->eval();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
void reset_eval(int n) {
|
||||||
|
this->reset = 1;
|
||||||
|
this->eval(n);
|
||||||
|
this->reset = 0;
|
||||||
|
}
|
||||||
|
bool is_posedge() {
|
||||||
|
// Will be posedge when eval is called
|
||||||
|
return T::clock == 0;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
23
npc/csrc_nvboard/Flow/CMakeLists.txt
Normal file
23
npc/csrc_nvboard/Flow/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,23 @@
|
||||||
|
include(ChiselBuild)
|
||||||
|
|
||||||
|
add_custom_command(
|
||||||
|
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/auto_bind.cpp
|
||||||
|
COMMAND auto_pin_bind ${CMAKE_SOURCE_DIR}/constr/${TOPMODULE}.nxdc ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/auto_bind.cpp
|
||||||
|
DEPENDS ${CMAKE_SOURCE_DIR}/constr/${TOPMODULE}.nxdc
|
||||||
|
)
|
||||||
|
|
||||||
|
add_executable(V${TOPMODULE}_nvboard
|
||||||
|
${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/auto_bind.cpp
|
||||||
|
main.cpp
|
||||||
|
)
|
||||||
|
|
||||||
|
verilate(V${TOPMODULE}_nvboard TRACE THREADS
|
||||||
|
TOP_MODULE ${TOPMODULE}
|
||||||
|
PREFIX V${TOPMODULE}
|
||||||
|
SOURCES ${CHISEL_OUTPUT_TOPMODULE}
|
||||||
|
INCLUDE_DIRS ${CHISEL_OUTPUT_DIR})
|
||||||
|
|
||||||
|
target_include_directories(V${TOPMODULE}_nvboard PRIVATE ${NVBOARD_INCLUDE_DIR} ${SDL2_INCLUDE_DIRS})
|
||||||
|
target_link_libraries(V${TOPMODULE}_nvboard PRIVATE ${NVBOARD_LIBRARY} SDL2::SDL2 SDL2_image::SDL2_image)
|
||||||
|
|
||||||
|
install(TARGETS V${TOPMODULE}_nvboard)
|
||||||
|
|
@ -1,99 +0,0 @@
|
||||||
{
|
|
||||||
"nodes": {
|
|
||||||
"flake-utils": {
|
|
||||||
"inputs": {
|
|
||||||
"systems": "systems"
|
|
||||||
},
|
|
||||||
"locked": {
|
|
||||||
"lastModified": 1710146030,
|
|
||||||
"narHash": "sha256-SZ5L6eA7HJ/nmkzGG7/ISclqe6oZdOZTNoesiInkXPQ=",
|
|
||||||
"owner": "numtide",
|
|
||||||
"repo": "flake-utils",
|
|
||||||
"rev": "b1d9ab70662946ef0850d488da1c9019f3a9752a",
|
|
||||||
"type": "github"
|
|
||||||
},
|
|
||||||
"original": {
|
|
||||||
"owner": "numtide",
|
|
||||||
"repo": "flake-utils",
|
|
||||||
"type": "github"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"nixpkgs": {
|
|
||||||
"locked": {
|
|
||||||
"lastModified": 1709961763,
|
|
||||||
"narHash": "sha256-6H95HGJHhEZtyYA3rIQpvamMKAGoa8Yh2rFV29QnuGw=",
|
|
||||||
"owner": "NixOS",
|
|
||||||
"repo": "nixpkgs",
|
|
||||||
"rev": "3030f185ba6a4bf4f18b87f345f104e6a6961f34",
|
|
||||||
"type": "github"
|
|
||||||
},
|
|
||||||
"original": {
|
|
||||||
"owner": "NixOS",
|
|
||||||
"ref": "nixos-unstable",
|
|
||||||
"repo": "nixpkgs",
|
|
||||||
"type": "github"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"nixpkgs-circt162": {
|
|
||||||
"locked": {
|
|
||||||
"lastModified": 1705645507,
|
|
||||||
"narHash": "sha256-tX3vipIAmNDBA8WNWG4oY4KyTfnm2YieTHO2BhG8ISA=",
|
|
||||||
"owner": "NixOS",
|
|
||||||
"repo": "nixpkgs",
|
|
||||||
"rev": "7995cae3ad60e3d6931283d650d7f43d31aaa5c7",
|
|
||||||
"type": "github"
|
|
||||||
},
|
|
||||||
"original": {
|
|
||||||
"owner": "NixOS",
|
|
||||||
"repo": "nixpkgs",
|
|
||||||
"rev": "7995cae3ad60e3d6931283d650d7f43d31aaa5c7",
|
|
||||||
"type": "github"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"nur-xin": {
|
|
||||||
"inputs": {
|
|
||||||
"nixpkgs": [
|
|
||||||
"nixpkgs"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"locked": {
|
|
||||||
"lastModified": 1707020873,
|
|
||||||
"narHash": "sha256-+dNltc7tjgTIyle/I/5siQ5IvPwu+R5Uf6e24CmjLNk=",
|
|
||||||
"ref": "refs/heads/master",
|
|
||||||
"rev": "8142717e7154dbaadee0679f0224fe75cebb1735",
|
|
||||||
"revCount": 147,
|
|
||||||
"type": "git",
|
|
||||||
"url": "https://git.xinyang.life/xin/nur.git"
|
|
||||||
},
|
|
||||||
"original": {
|
|
||||||
"type": "git",
|
|
||||||
"url": "https://git.xinyang.life/xin/nur.git"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"root": {
|
|
||||||
"inputs": {
|
|
||||||
"flake-utils": "flake-utils",
|
|
||||||
"nixpkgs": "nixpkgs",
|
|
||||||
"nixpkgs-circt162": "nixpkgs-circt162",
|
|
||||||
"nur-xin": "nur-xin"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"systems": {
|
|
||||||
"locked": {
|
|
||||||
"lastModified": 1681028828,
|
|
||||||
"narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=",
|
|
||||||
"owner": "nix-systems",
|
|
||||||
"repo": "default",
|
|
||||||
"rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e",
|
|
||||||
"type": "github"
|
|
||||||
},
|
|
||||||
"original": {
|
|
||||||
"owner": "nix-systems",
|
|
||||||
"repo": "default",
|
|
||||||
"type": "github"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"root": "root",
|
|
||||||
"version": 7
|
|
||||||
}
|
|
||||||
116
npc/flake.nix
116
npc/flake.nix
|
|
@ -1,116 +0,0 @@
|
||||||
{
|
|
||||||
inputs = {
|
|
||||||
nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
|
|
||||||
nixpkgs-circt162.url = "github:NixOS/nixpkgs/7995cae3ad60e3d6931283d650d7f43d31aaa5c7";
|
|
||||||
flake-utils.url = "github:numtide/flake-utils";
|
|
||||||
nur-xin = {
|
|
||||||
url = "git+https://git.xinyang.life/xin/nur.git";
|
|
||||||
inputs.nixpkgs.follows = "nixpkgs";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
outputs = { self, ... }@inputs: with inputs;
|
|
||||||
flake-utils.lib.eachDefaultSystem (system:
|
|
||||||
let
|
|
||||||
pkgs = import nixpkgs { inherit system; config.allowUnfree = true; }//
|
|
||||||
{ nur.xin = nur-xin.legacyPackages.${system}; };
|
|
||||||
in
|
|
||||||
{
|
|
||||||
devShells.default = with pkgs; mkShell {
|
|
||||||
CHISEL_FIRTOOL_PATH = "${nixpkgs-circt162.legacyPackages.${system}.circt}/bin";
|
|
||||||
packages = [
|
|
||||||
clang-tools
|
|
||||||
# rnix-lsp
|
|
||||||
coursier
|
|
||||||
espresso
|
|
||||||
|
|
||||||
gdb
|
|
||||||
jre
|
|
||||||
|
|
||||||
gtkwave
|
|
||||||
];
|
|
||||||
|
|
||||||
inputsFrom = [ self.packages.${system}.default ];
|
|
||||||
};
|
|
||||||
packages.default = with pkgs; clangStdenv.mkDerivation {
|
|
||||||
name = "npc";
|
|
||||||
version = "0.0.1";
|
|
||||||
src = ./.;
|
|
||||||
nativeBuildInputs = [
|
|
||||||
cmake
|
|
||||||
sbt
|
|
||||||
nur.xin.nvboard
|
|
||||||
nixpkgs-circt162.legacyPackages.${system}.circt
|
|
||||||
yosys
|
|
||||||
];
|
|
||||||
buildInputs = [
|
|
||||||
verilator
|
|
||||||
nur.xin.nvboard
|
|
||||||
];
|
|
||||||
|
|
||||||
NEMU_HOME="/home/xin/repo/ysyx-workbench/nemu";
|
|
||||||
};
|
|
||||||
|
|
||||||
# This version (1.43.0) of circt does not exist in nixpkgs
|
|
||||||
# and Chisel 5.1.0 specifically build against it, so here we are.
|
|
||||||
# Ref: https://github.com/NixOS/nixpkgs/blob/b6465c8/pkgs/development/compilers/circt/default.nix
|
|
||||||
packages.circt =
|
|
||||||
with pkgs;
|
|
||||||
let
|
|
||||||
pythonEnv = python3.withPackages (ps: [ ps.psutil ]);
|
|
||||||
in
|
|
||||||
stdenv.mkDerivation rec {
|
|
||||||
pname = "circt";
|
|
||||||
version = "1.43.0";
|
|
||||||
src = fetchFromGitHub {
|
|
||||||
owner = "llvm";
|
|
||||||
repo = "circt";
|
|
||||||
rev = "firtool-${version}";
|
|
||||||
sha256 = "sha256-RkjigboswLkLgLkgOGahQLIygCkC3Q9rbVw3LqIzREY=";
|
|
||||||
fetchSubmodules = true;
|
|
||||||
};
|
|
||||||
|
|
||||||
requiredSystemFeatures = [ "big-parallel" ];
|
|
||||||
|
|
||||||
nativeBuildInputs = [ cmake ninja git pythonEnv ];
|
|
||||||
|
|
||||||
cmakeDir = "../llvm/llvm";
|
|
||||||
cmakeFlags = [
|
|
||||||
"-DLLVM_ENABLE_BINDINGS=OFF"
|
|
||||||
"-DLLVM_ENABLE_OCAMLDOC=OFF"
|
|
||||||
"-DLLVM_BUILD_EXAMPLES=OFF"
|
|
||||||
"-DLLVM_OPTIMIZED_TABLEGEN=ON"
|
|
||||||
"-DLLVM_ENABLE_PROJECTS=mlir"
|
|
||||||
"-DLLVM_EXTERNAL_PROJECTS=circt"
|
|
||||||
"-DLLVM_EXTERNAL_CIRCT_SOURCE_DIR=.."
|
|
||||||
"-DCIRCT_LLHD_SIM_ENABLED=OFF"
|
|
||||||
];
|
|
||||||
|
|
||||||
LIT_FILTER_OUT = if stdenv.cc.isClang then "CIRCT :: Target/ExportSystemC/.*\.mlir" else null;
|
|
||||||
|
|
||||||
preConfigure = ''
|
|
||||||
find ./test -name '*.mlir' -exec sed -i 's|/usr/bin/env|${coreutils}/bin/env|g' {} \;
|
|
||||||
'';
|
|
||||||
|
|
||||||
installPhase = ''
|
|
||||||
runHook preInstall
|
|
||||||
mkdir -p $out/bin
|
|
||||||
mv bin/{{fir,hls}tool,circt-{as,dis,lsp-server,opt,reduce,translate}} $out/bin
|
|
||||||
runHook postInstall
|
|
||||||
'';
|
|
||||||
|
|
||||||
doCheck = true;
|
|
||||||
checkTarget = "check-circt check-circt-integration";
|
|
||||||
|
|
||||||
meta = {
|
|
||||||
description = "Circuit IR compilers and tools";
|
|
||||||
homepage = "https://circt.org/";
|
|
||||||
license = lib.licenses.asl20;
|
|
||||||
maintainers = with lib.maintainers; [ sharzy ];
|
|
||||||
platforms = lib.platforms.all;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
}
|
|
||||||
);
|
|
||||||
}
|
|
||||||
|
|
||||||
126
npc/include/difftest.hpp
Normal file
126
npc/include/difftest.hpp
Normal file
|
|
@ -0,0 +1,126 @@
|
||||||
|
#ifndef _DIFFTEST_DIFFTEST_H_
|
||||||
|
#define _DIFFTEST_DIFFTEST_H_
|
||||||
|
#include <cassert>
|
||||||
|
#include <cstdint>
|
||||||
|
#include <cstdlib>
|
||||||
|
#include <dlfcn.h>
|
||||||
|
#include <filesystem>
|
||||||
|
#include <functional>
|
||||||
|
#include <iostream>
|
||||||
|
#include <memory>
|
||||||
|
|
||||||
|
using paddr_t = uint32_t;
|
||||||
|
enum { DIFFTEST_FROM_REF, DIFFTEST_TO_REF };
|
||||||
|
|
||||||
|
struct DifftestInterface {
|
||||||
|
using memcpy_t = void (*)(paddr_t, void *, size_t, bool);
|
||||||
|
using regcpy_t = void (*)(void *, bool);
|
||||||
|
using exec_t = void (*)(uint64_t);
|
||||||
|
using init_t = void (*)(int);
|
||||||
|
std::function<void(paddr_t, void *, size_t, bool)> memcpy;
|
||||||
|
std::function<void(void *, bool)> regcpy;
|
||||||
|
std::function<void(uint64_t)> exec;
|
||||||
|
std::function<void(int)> init;
|
||||||
|
|
||||||
|
DifftestInterface(memcpy_t memcpy, regcpy_t regcpy, exec_t exec, init_t init)
|
||||||
|
: memcpy(memcpy), regcpy(regcpy), exec(exec), init(init){};
|
||||||
|
|
||||||
|
// using fs = std::filesystem::path;
|
||||||
|
DifftestInterface(std::filesystem::path lib_file) {
|
||||||
|
void *handle = dlopen(lib_file.c_str(), RTLD_LAZY);
|
||||||
|
assert(handle != nullptr);
|
||||||
|
memcpy = (memcpy_t)dlsym(handle, "difftest_memcpy");
|
||||||
|
assert(memcpy);
|
||||||
|
regcpy = (regcpy_t)dlsym(handle, "difftest_regcpy");
|
||||||
|
assert(regcpy);
|
||||||
|
exec = (exec_t)dlsym(handle, "difftest_exec");
|
||||||
|
assert(exec);
|
||||||
|
init = (init_t)dlsym(handle, "difftest_init");
|
||||||
|
assert(init);
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
template <typename S> class Difftest {
|
||||||
|
const DifftestInterface &ref;
|
||||||
|
std::unique_ptr<S> ref_state;
|
||||||
|
const DifftestInterface &dut;
|
||||||
|
std::unique_ptr<S> dut_state;
|
||||||
|
|
||||||
|
public:
|
||||||
|
Difftest(const DifftestInterface &dut, const DifftestInterface &ref,
|
||||||
|
void *mem, size_t n, std::unique_ptr<S> ref_state = nullptr,
|
||||||
|
std::unique_ptr<S> dut_state = nullptr)
|
||||||
|
: ref(ref), dut(dut), ref_state(std::move(ref_state)),
|
||||||
|
dut_state(std::move(dut_state)) {
|
||||||
|
if (ref_state == nullptr)
|
||||||
|
this->ref_state = std::make_unique<S>();
|
||||||
|
if (dut_state == nullptr)
|
||||||
|
this->dut_state = std::make_unique<S>();
|
||||||
|
ref.init(0);
|
||||||
|
dut.init(0);
|
||||||
|
fetch_state();
|
||||||
|
paddr_t reset_vector = 0x80000000;
|
||||||
|
ref.memcpy(reset_vector, mem, n, DIFFTEST_TO_REF);
|
||||||
|
dut.memcpy(reset_vector, mem, n, DIFFTEST_TO_REF);
|
||||||
|
};
|
||||||
|
|
||||||
|
void fetch_state() {
|
||||||
|
ref.regcpy(ref_state.get(), DIFFTEST_FROM_REF);
|
||||||
|
dut.regcpy(dut_state.get(), DIFFTEST_FROM_REF);
|
||||||
|
}
|
||||||
|
|
||||||
|
void step(uint64_t n) {
|
||||||
|
ref.exec(n);
|
||||||
|
dut.exec(n);
|
||||||
|
fetch_state();
|
||||||
|
if (*ref_state != *dut_state) {
|
||||||
|
std::cout << *this;
|
||||||
|
exit(EXIT_FAILURE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
friend std::ostream &operator<<(std::ostream &os, const Difftest<S> &d) {
|
||||||
|
os << "REF state:\n"
|
||||||
|
<< *d.ref_state << "DUT state:\n"
|
||||||
|
<< *d.dut_state << std::endl;
|
||||||
|
return os;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
template <typename R, size_t nr_reg> struct CPUStateBase {
|
||||||
|
R reg[nr_reg] = {0};
|
||||||
|
paddr_t pc = 0x80000000;
|
||||||
|
CPUStateBase() {
|
||||||
|
for (int i = 0; i < nr_reg; i++)
|
||||||
|
reg[i] = 0;
|
||||||
|
}
|
||||||
|
bool operator==(const CPUStateBase &other) const {
|
||||||
|
if (pc != other.pc)
|
||||||
|
return false;
|
||||||
|
for (int i = 0; i < nr_reg; ++i) {
|
||||||
|
if (reg[i] != other.reg[i])
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
bool operator!=(const CPUStateBase &other) const {
|
||||||
|
return !(*this == other); // Reuse the == operator for != implementation
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
template <typename R, size_t nr_reg>
|
||||||
|
std::ostream &operator<<(std::ostream &os, const CPUStateBase<R, nr_reg> &cpu) {
|
||||||
|
os << "PC: " << std::hex << cpu.pc << std::endl;
|
||||||
|
for (int i = 0; i < nr_reg; i++) {
|
||||||
|
os << "reg " << std::dec << std::setw(2) << i << ":" << std::hex
|
||||||
|
<< std::setw(10) << cpu.reg[i];
|
||||||
|
if (i % 4 == 3) {
|
||||||
|
os << std::endl;
|
||||||
|
} else {
|
||||||
|
os << " | ";
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return os;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -1,10 +1,17 @@
|
||||||
00114113
|
00110113
|
||||||
00114113
|
00110113
|
||||||
00114113
|
00110113
|
||||||
00114113
|
00110113
|
||||||
00114113
|
00110113
|
||||||
00114113
|
00110113
|
||||||
00114113
|
00110113
|
||||||
00114113
|
00110113
|
||||||
00114113
|
00110113
|
||||||
00114113
|
00110113
|
||||||
|
00110113
|
||||||
|
00110113
|
||||||
|
00110113
|
||||||
|
00110113
|
||||||
|
00110113
|
||||||
|
00110113
|
||||||
|
00110113
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue