Add difftest support to npc #3

Merged
xin merged 10 commits from npc-debug-tools into master 2024-04-05 05:14:45 +00:00
3 changed files with 95 additions and 51 deletions
Showing only changes of commit db66021248 - Show all commits

View file

@ -83,7 +83,7 @@ static void execute(uint64_t n) {
g_nr_guest_inst ++;
trace_and_difftest(&s, cpu.pc);
if (wp_eval_all()) {
puts(logbuf[logbuf_rear]);
IFDEF(CONFIG_ITRACE, puts(logbuf[logbuf_rear]));
break;
}
if (nemu_state.state != NEMU_RUNNING) break;
@ -132,7 +132,7 @@ void cpu_exec(uint64_t n) {
ANSI_FMT("HIT BAD TRAP", ANSI_FG_RED))),
nemu_state.halt_pc);
if(nemu_state.halt_ret != 0) {
log_itrace_print();
IFDEF(CONFIG_ITRACE, log_itrace_print());
}
} // fall through
case NEMU_QUIT: statistic();

View file

@ -1,7 +1,7 @@
cmake_minimum_required(VERSION 3.26)
project(flow)
set (CMAKE_CXX_STANDARD 14)
set (CMAKE_CXX_STANDARD 17)
cmake_policy(SET CMP0144 NEW)
include(CMakeDependentOption)

View file

@ -1,3 +1,8 @@
#include "VFlow___024root.h"
#include "tracer.h"
#include <array>
#include <cstddef>
#include <filesystem>
#include <vpi_user.h>
#include <VFlow.h>
#include <cstdlib>
@ -13,40 +18,90 @@
std::vector<vpiHandle> regsHandle;
int regs[32];
static void init_vpi_regs() {
std::string regfile = "TOP.Flow.reg_0.regFile_";
for(int i = 0; i < 32; i++) {
std::string regname = regfile + std::to_string(i);
vpiHandle vh = vpi_handle_by_name((PLI_BYTE8 *)regname.c_str(), NULL);
regsHandle.push_back(vh);
template <class T>
class Tracer {
#ifdef VERILATOR_TRACE
std::shared_ptr<T> top;
std::unique_ptr<VerilatedVcdC> m_trace;
uint64_t time = 0;
#endif
public:
Tracer(std::shared_ptr<T> top, std::filesystem::path wavefile) {
#ifdef VERILATOR_TRACE
top = top;
Verilated::traceEverOn(true);
m_trace = std::make_unique<VerilatedVcdC>();
top->trace(m_trace.get(), 5);
m_trace->open(wavefile.c_str());
#endif
}
~Tracer() {
#ifdef VERILATOR_TRACE
m_trace->close();
#endif
}
static void init_vpi() {
init_vpi_regs();
/**
* Dump signals to waveform file. Must be called once after every top->eval() call.
*/
void update() {
#ifdef VERILATOR_TRACE
m_trace->dump(time++);
#endif
}
static int vpi_get_int(vpiHandle vh) {
s_vpi_value v;
v.format = vpiIntVal;
vpi_get_value(vh, &v);
return v.value.integer;
}
static void update_regs() {
for(int i = 0; i < 32; i++) {
regs[i] = vpi_get_int(regsHandle[i]);
};
template <typename T, std::size_t nr>
class _RegistersBase {
std::array<T, nr> regs;
virtual T fetch_reg(size_t id);
public:
void update() {
for(int i = 0; i < regs.size(); i++) {
regs[i] = fetch_reg(i);
}
}
static void print_regs() {
for(int i = 0; i < 32; i++) {
void print_regs() {
for(int i = 0; i < regs.size(); i++) {
printf("%d: %d\t", i, regs[i]);
if(i % 8 == 7) putchar('\n');
}
putchar('\n');
}
};
template <typename T, std::size_t nr>
class _RegistersVPI : public _RegistersBase<T, nr> {
std::array<vpiHandle, nr> reg_handles;
T fetch_reg(size_t id) {
s_vpi_value v;
v.format = vpiIntVal;
vpi_get_value(reg_handles[id], &v);
return v.value.integer;
}
public:
_RegistersVPI<T, nr>(const std::string regs_prefix) {
for(int i = 0; i < nr; i++) {
std::string regname = regs_prefix + std::to_string(i);
vpiHandle vh = vpi_handle_by_name((PLI_BYTE8 *)regname.c_str(), NULL);
reg_handles[i] = vh;
}
}
};
template <typename T, std::size_t n>
class Memory {
std::array<T, n> mem;
size_t addr_to_index(size_t addr) {
// Linear mapping
return addr - 0x80000000;
}
public:
const T& operator[](size_t addr) {
return mem[addr_to_index(index)];
}
};
typedef _RegistersVPI<uint32_t, 32> Registers;
static int sim_time = 0;
int main(int argc, char **argv, char **env) {
@ -54,33 +109,22 @@ int main(int argc, char **argv, char **env) {
int posedge_cnt = 0;
Verilated::commandArgs(argc, argv);
std::unique_ptr<VFlow> top{new VFlow};
Verilated::traceEverOn(true);
VerilatedVcdC *m_trace = new VerilatedVcdC;
#ifdef VERILATOR_TRACE
top->trace(m_trace, 5);
m_trace->open("waveform.vcd");
#endif
auto top = std::make_shared<VFlow>();
auto top_tracer = std::make_unique<Tracer<VFlow>>(top, "waveform.vcd");
init_vpi();
Registers regs("TOP.Flow.reg_0.regFile_");
top->reset = 0;
for (sim_time = 10; sim_time < MAX_SIM_TIME; sim_time++) {
top->eval();
for (sim_time = 10; sim_time < MAX_SIM_TIME; sim_time++) {
top->clock = !top->clock;
if(top->clock == 1) {
// Posedge
++posedge_cnt;
update_regs();
print_regs();
regs.update();
regs.print_regs();
}
#ifdef VERILATOR_TRACE
m_trace->dump(sim_time);
#endif
top->eval();
}
#ifdef VERILATOR_TRACE
m_trace->close();
#endif
exit(EXIT_SUCCESS);
}