npc,feat: add csr

.scalafmt.conf

@@ -0,0 +1,2 @@
+version = 3.7.17
+runner.dialect = scala213source3

flake.nix

@@ -50,6 +50,13 @@
                 enable = true;
                 types_or = pkgs.lib.mkForce [ "c" "c++" ];
               };
+              scalafmt = {
+                enable = true;
+                package = pkgs.scalafmt;
+                name = "Scalafmt";
+                types = [ "scala" ];
+                entry = "${pkgs.scalafmt}/bin/scalafmt --non-interactive";
+              };
             };
           };
         };

npc/core/build.sbt

@@ -1,7 +1,6 @@
 ThisBuild / scalaVersion := "2.13.12"
 ThisBuild / version := "0.1.0"
 
-
 val chiselVersion = "6.2.0"
 val circeVersion = "0.14.1"
 
@@ -12,7 +11,7 @@ lazy val root = (project in file("."))
       "org.chipsalliance" %% "chisel" % chiselVersion,
       "edu.berkeley.cs" %% "chiseltest" % "6.0.0" % "test",
       "com.chuusai" %% "shapeless" % "2.3.3",
-      "com.github.scopt" %% "scopt" % "4.1.0",
+      "com.github.scopt" %% "scopt" % "4.1.0"
     ) ++ Seq(
       "io.circe" %% "circe-core",
       "io.circe" %% "circe-generic",
@@ -23,7 +22,9 @@ lazy val root = (project in file("."))
       "-deprecation",
       "-feature",
       "-Xcheckinit",
-      "-Ymacro-annotations",
+      "-Ymacro-annotations"
     ),
-    addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full),
+    addCompilerPlugin(
+      "org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full
+    )
   )

npc/core/src/main/scala/components/CSR.scala

@@ -0,0 +1,108 @@
+package flow.components
+
+import chisel3._
+import chisel3.util.log2Ceil
+import scala.reflect.runtime.universe._
+import cats.instances.MapInstances
+import dataclass.data
+import chisel3.util.experimental.decode.{decoder, TruthTable}
+import shapeless.HNil
+import flow.Params
+import chisel3.util.BitPat
+import chisel3.util.Fill
+
+class CSRControlInterface extends Bundle {
+  object csrRead extends ChiselEnum {
+    val csrReadDisabled, csrReadEnabled = Value
+  }
+
+  object csrWrite extends ChiselEnum {
+    val csrWriteDisabled, csrWriteEnabled = Value
+  }
+
+  val readEnable = Input(csrRead())
+  val writeEnable = Input(csrWrite())
+
+  def ctrlBindPorts = {
+    readEnable :: writeEnable :: HNil
+  }
+}
+
+class CSRCore(implicit val p: Params) extends Module {
+  val control = IO(new CSRControlInterface)
+
+  val in = IO(new Bundle {
+    val csrAddr = Input(UInt(p.csrAddrWidth))
+    val writeData = Input(UInt(p.XLEN))
+  })
+
+  val out = IO(new Bundle {
+    val readData = Output(UInt(p.XLEN))
+    val readValid = Output(Bool())
+  })
+
+  implicit class fromChiselEnumToBool[T <: EnumType](x: T) {
+    def B: Bool = {
+      x.asUInt =/= 0.U
+    }
+  }
+
+  val nameToAddr = Map(
+    "mstatus" -> 0x300,
+    "mtvec" -> 0x305,
+    "mie" -> 0x304,
+    "mepc" -> 0x341,
+    "mcause" -> 0x342,
+    "mtval" -> 0x343,
+    "mip" -> 0x344
+  )
+  val csrSize = nameToAddr.size
+
+  val addrToIndex = nameToAddr.zipWithIndex
+    .map(x => {
+      val (name: String, csrAddr: Int) = x._1
+      val index = x._2
+
+      csrAddr -> index
+    })
+    .toMap
+  val indexToAddr = addrToIndex.map(_.swap)
+
+  val csrIndexWidth = log2Ceil(csrSize).W
+
+  private val align = (x: UInt, w: Width) => BitPat(x.litValue.U(w))
+  val csrIndex = decoder(
+    in.csrAddr,
+    TruthTable(
+      addrToIndex.map(x =>
+        // Addr                              Index
+        (align(x._1.U, p.csrAddrWidth), align(x._2.U, csrIndexWidth))
+      ),
+      align(addrToIndex.head._2.U, csrIndexWidth)
+    )
+  )
+
+  val csrIndexValid = !(
+    csrIndex === BitPat(0.U) &&
+      in.csrAddr =/= align(indexToAddr(0).U, p.csrAddrWidth)
+  )
+
+  val regs = RegInit(VecInit(Seq.fill(csrSize)(0.U(p.XLEN))))
+
+  val regReadValue = regs(csrIndex)
+
+  val delayWriteData = RegNext(in.writeData, 0.U(p.XLEN))
+  val delayWriteEnable = RegNext(control.writeEnable)
+
+  when(control.writeEnable.B) {
+    regs(csrIndex) := delayWriteData
+  }
+
+  when(control.readEnable.B) {
+    out.readData := regReadValue
+    out.readValid := true.B && csrIndexValid
+  } otherwise {
+    out.readData := 0.U(p.XLEN)
+    out.readValid := false.B && csrIndexValid
+  }
+}

npc/core/src/main/scala/components/Mem.scala

@@ -24,7 +24,8 @@ class RamControlInterface(addrWidth: Int) extends Bundle {
 /* FIXME: Extends here might not be the best solution.
  *        We need a way to merge two bundles together
  */
-class RamInterface[T <: Data](tpe: T, addrWidth: Int) extends RamControlInterface(addrWidth) {
+class RamInterface[T <: Data](tpe: T, addrWidth: Int)
+    extends RamControlInterface(addrWidth) {
   val clock = Input(Clock())
   val reset = Input(Reset())
   val writeAddr = Input(UInt(addrWidth.W))

npc/core/src/main/scala/components/ProgramCounter.scala

@@ -30,11 +30,11 @@ class ProgramCounter[T <: UInt](tpe: T) extends Module {
 
 //   pc := in.pcSrcs(control.srcSelect.asUInt)
   import control.SrcSelect._
-  when( control.useImmB === true.B ) {
+  when(control.useImmB === true.B) {
     pc_reg := pc_reg + in.immB
-  }. elsewhen( control.srcSelect === pStaticNpc) {
+  }.elsewhen(control.srcSelect === pStaticNpc) {
     pc_reg := pc_reg + 4.U
-  }. elsewhen( control.srcSelect === pExeOut) {
+  }.elsewhen(control.srcSelect === pExeOut) {
     pc_reg := in.exeOut
   }
   out := pc_reg

npc/core/src/main/scala/components/RegisterFile.scala

@@ -5,7 +5,7 @@ import chisel3.util.log2Ceil
 import chisel3.util.UIntToOH
 import chisel3.util.MuxLookup
 import chisel3.experimental.Trace._
-import shapeless.{ HList, HNil, :: }
+import shapeless.{HList, HNil, ::}
 
 class RegControl extends Bundle {
   object WriteSelect extends ChiselEnum {
@@ -21,7 +21,8 @@ class RegControl extends Bundle {
   traceName(writeEnable)
 }
 
-class RegisterFile[T <: Data](tpe: T, regCount: Int, numReadPorts: Int) extends Module {
+class RegisterFile[T <: Data](tpe: T, regCount: Int, numReadPorts: Int)
+    extends Module {
   require(numReadPorts >= 0)
   val control = IO(new RegControl)
   val dataAddrWidth = log2Ceil(regCount).W
@@ -40,7 +41,10 @@ class RegisterFile[T <: Data](tpe: T, regCount: Int, numReadPorts: Int) extends
 
   for ((reg, i) <- regFile.zipWithIndex.tail) {
     reg := Mux(
-      writeAddrOH(i.U(log2Ceil(regCount).W)) && control.writeEnable, in.writeData(control.writeSelect.asUInt), reg)
+      writeAddrOH(i.U(log2Ceil(regCount).W)) && control.writeEnable,
+      in.writeData(control.writeSelect.asUInt),
+      reg
+    )
   }
   regFile(0) := 0.U
 

npc/core/src/main/scala/top/ArgParse.scala

@@ -1,13 +1,13 @@
 package flow
 
-import scopt.{ OParser, DefaultOEffectSetup }
+import scopt.{OParser, DefaultOEffectSetup}
 import java.io.File
 
 case class CliOptions(
     targetDir: File = new File("."),
     configFile: Option[File] = None,
     argsFile: Option[File] = None,
-    verilatorConfigFileOut: File = new File("conf.vlt"),
+    verilatorConfigFileOut: File = new File("conf.vlt")
 ) {
   val builder = OParser.builder[CliOptions]
   val parser = {
@@ -33,14 +33,19 @@ case class CliOptions(
   def parse(args: Array[String]): CliOptions = {
     OParser.runParser(parser, args, CliOptions()) match {
       case (result, effects) =>
-        OParser.runEffects(effects, new DefaultOEffectSetup {
+        OParser.runEffects(
+          effects,
+          new DefaultOEffectSetup {
             // ignore terminate
             override def terminate(exitState: Either[String, Unit]): Unit = ()
-        })
+          }
+        )
 
         result match {
           case Some(cliOptions: CliOptions) => { return cliOptions }
-          case _ => { throw new IllegalArgumentException("Wrong command line argument") }
+          case _ => {
+            throw new IllegalArgumentException("Wrong command line argument")
+          }
         }
     }
   }

npc/core/src/main/scala/top/Config.scala

@@ -3,14 +3,20 @@ package flow
 import io.circe.generic.JsonCodec
 
 // Which group of signals to trace
-@JsonCodec case class TraceConfig (
+@JsonCodec case class TraceConfig(
     enable: Boolean = false,
     registers: Array[Int] = Array(),
-  mem: Array[(Int, Int)] = Array(),
+    mem: Array[(Int, Int)] = Array()
 )
 
 @JsonCodec case class Config(
     // Whether to enable Difftest
     enableDifftest: Boolean = true,
-  traceConfig: TraceConfig = TraceConfig(),
+    traceConfig: TraceConfig = TraceConfig()
+)
+
+import chisel3._
+case class Params(
+    XLEN: Width,
+    csrAddrWidth: Width = 12.W
 )

npc/core/src/main/scala/top/FlowMain.scala

@@ -8,7 +8,7 @@ import chisel3.experimental.Trace._
 import shapeless.{HNil, ::}
 import shapeless.HList
 import shapeless.ops.coproduct.Prepend
-import chisel3.util.{ BinaryMemoryFile, HexMemoryFile }
+import chisel3.util.{BinaryMemoryFile, HexMemoryFile}
 
 import chisel3.experimental.Trace
 import scala.collection.IndexedSeqView
@@ -18,6 +18,7 @@ import flow.components.RamControlInterface
 object RV32Inst {
   private val bp = BitPat
 
+  // format: off
   val lui    = this.bp("b???????_?????_?????_???_?????_01101_11")
   val auipc  = this.bp("b???????_?????_?????_???_?????_00101_11")
 
@@ -72,22 +73,27 @@ object RV32Inst {
   val remu   = this.bp("b0000001_?????_?????_111_?????_01100_11")
 
   val inv    = this.bp("b???????_?????_?????_???_?????_?????_??")
+  // format: on
 }
 
 import flow.components.{RegControl, PcControlInterface, ALUControlInterface}
 class Control(width: Int) extends RawModule {
   // Helpers
-  class WrapList[T](vl: T) { type Type = T; val v = vl}
+  class WrapList[T](vl: T) { type Type = T; val v = vl }
   object wrap extends Poly1 {
     implicit def default[A] = at[A](Right(_).withLeft[Int])
   }
   def lit(x: Element) = { x.litValue.toInt }
   def toBits(t: dst.Type): BitPat = {
     val list = t.toList
-    list.map(e => e match {
+    list
+      .map(e =>
+        e match {
           case Right(x) => BitPat(lit(x).U(x.getWidth.W))
           case Left(x)  => BitPat.dontCare(x)
-    }).reduceLeft(_ ## _)
+        }
+      )
+      .reduceLeft(_ ## _)
   }
   val r = Right
   def l[T <: Any](x: T) = x match {
@@ -103,11 +109,12 @@ class Control(width: Int) extends RawModule {
   val alu = IO(Flipped(new ALUControlInterface))
   val ram = IO(Flipped(new RamControlInterface(32)))
 
-  val dst = new WrapList((
+  val dst = new WrapList(
-    reg.ctrlBindPorts ++
+    (reg.ctrlBindPorts ++
       pc.ctrlBindPorts ++
       alu.ctrlBindPorts ++
-    ram.ctrlBindPorts).map(wrap))
+      ram.ctrlBindPorts).map(wrap)
+  )
 
   val dstList = dst.v.toList
   val controlWidth = dstList.map(_.toOption.get.getWidth).reduce(_ + _)
@@ -124,209 +131,286 @@ class Control(width: Int) extends RawModule {
   import alu.SrcBSelect._
   import pc._
   import RV32Inst._
+  // format: off
   val ControlMapping: Array[(BitPat, dst.Type)] = Array(
     //     Regs | writeEnable :: writeSelect :: HNil
     //     PC   | useImmB :: srcSelect :: HNil
     //     Exe  | op :: srcASelect :: srcBSelect :: signExt :: HNil
     //     Mem  | valid :: writeMask :: writeEnable :: HNil
 
-    (lui   , (r(true.B)     :: r(rAluOut)  ::
+    (lui   , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc)::
       r(aOpAdd)     :: r(aSrcAZero)  :: r(aSrcBImmU) :: r(false.B) ::
-              r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (auipc , (r(true.B)     :: r(rAluOut)  ::
+    (auipc , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc)::
       r(aOpAdd)     :: r(aSrcAPc)  :: r(aSrcBImmU) :: r(false.B) ::
-              r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
     // ---- Control Transfer Instructions ----
-    (jal   , (r(true.B)     :: r(rNpc)     ::
+    (jal   , (
+      r(true.B)     :: r(rNpc)     ::
       r(false.B)    :: r(pExeOut)  ::
       r(aOpAdd)     :: r(aSrcAPc)  :: r(aSrcBImmJ) :: r(false.B) ::
-              r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (jalr  , (r(true.B)     :: r(rNpc)     ::
+    (jalr  , (
+      r(true.B)     :: r(rNpc)     ::
       r(false.B)    :: r(pExeOut)    ::
       r(aOpAdd)     :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) ::
-              r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (beq   , (r(false.B)    :: l(WriteSelect) ::
+    (beq   , (
+      r(false.B)    :: l(WriteSelect) ::
       r(true.B)     :: r(pStaticNpc)     ::
       r(aOpSlt)     :: r(aSrcARs1)  :: r(aSrcBRs2) :: l(Bool())    ::
-              r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (bne   , (r(false.B)    :: l(WriteSelect) ::
+    (bne   , (
+      r(false.B)    :: l(WriteSelect) ::
       r(true.B)     :: r(pStaticNpc)     ::
       r(aOpSlt)     :: r(aSrcARs1)  :: r(aSrcBRs2) :: l(Bool())    ::
-              r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (blt   , (r(false.B)    :: l(WriteSelect) ::
+    (blt   , (
+      r(false.B)    :: l(WriteSelect) ::
       r(true.B)     :: r(pStaticNpc)     ::
       r(aOpSlt)     :: r(aSrcARs1)  :: r(aSrcBRs2) :: r(true.B)  ::
-              r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (bge   , (r(false.B)    :: l(WriteSelect) ::
+    (bge   , (
+      r(false.B)    :: l(WriteSelect) ::
       r(true.B)     :: r(pStaticNpc)     ::
       r(aOpSlt)     :: r(aSrcARs1)  :: r(aSrcBRs2) :: r(true.B)  ::
-              r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (bltu  , (r(false.B)    :: l(WriteSelect)::
+    (bltu  , (
+      r(false.B)    :: l(WriteSelect)::
       r(true.B)     :: r(pStaticNpc)    ::
       r(aOpSltu)     :: r(aSrcARs1)    :: r(aSrcBRs2) :: r(false.B) ::
-              r(false.B)    :: l(UInt(4.W))  :: r(false.B)   :: HNil)),
+      r(false.B)    :: l(UInt(4.W))  :: r(false.B)   :: HNil
+    )),
 
-    (bgeu  , (r(false.B)    :: l(WriteSelect)::
+    (bgeu  , (
+      r(false.B)    :: l(WriteSelect)::
       r(true.B)     :: r(pStaticNpc)    ::
       r(aOpSltu)     :: r(aSrcARs1)    :: r(aSrcBRs2) :: r(false.B) ::
-              r(false.B)    :: l(UInt(4.W))  :: r(false.B)   :: HNil)),
+      r(false.B)    :: l(UInt(4.W))  :: r(false.B)   :: HNil
+    )),
 
     // ---- Memory Access Instructions ----
 
-    (lb    , (r(true.B)     :: r(rMemOut)    ::
+    (lb    , (
+      r(true.B)     :: r(rMemOut)    ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmI) :: l(Bool()) ::
-              r(true.B)     :: r(1.U(4.W))  :: r(false.B)   :: HNil)),
+      r(true.B)     :: r(1.U(4.W))  :: r(false.B)   :: HNil
+    )),
 
-    (lbu    , (r(true.B)    :: r(rMemOut)    ::
+    (lbu   , (
+      r(true.B)    :: r(rMemOut)    ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmI) :: l(Bool()) ::
-              r(true.B)     :: r(0.U(4.W))  :: r(false.B)   :: HNil)),
+      r(true.B)     :: r(0.U(4.W))  :: r(false.B)   :: HNil
+    )),
 
-    (lh     , (r(true.B)    :: r(rMemOut)    ::
+    (lh     , (
+      r(true.B)    :: r(rMemOut)    ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmI) :: l(Bool()) ::
-              r(true.B)     :: r(3.U(4.W))  :: r(false.B)   :: HNil)),
+      r(true.B)     :: r(3.U(4.W))  :: r(false.B)   :: HNil
+    )),
 
-    (lhu    , (r(true.B)    :: r(rMemOut)    ::
+    (lhu    , (
+      r(true.B)    :: r(rMemOut)    ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmI) :: l(Bool()) ::
-              r(true.B)     :: r(2.U(4.W))  :: r(false.B)   :: HNil)),
+      r(true.B)     :: r(2.U(4.W))  :: r(false.B)   :: HNil
+    )),
 
-    (lw    , (r(true.B)     :: r(rMemOut)    ::
+    (lw    , (
+      r(true.B)     :: r(rMemOut)    ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmI) :: l(Bool()) ::
-              r(true.B)     :: r(14.U(4.W))  :: r(false.B)   :: HNil)),
+      r(true.B)     :: r(14.U(4.W))  :: r(false.B)   :: HNil
+    )),
 
-    (sb    , (r(false.B)    :: l(WriteSelect)::
+    (sb    , (
+      r(false.B)    :: l(WriteSelect)::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmS) :: l(Bool()) ::
-              r(true.B)     :: r(1.U(4.W))   :: r(true.B)   :: HNil)),
+      r(true.B)     :: r(1.U(4.W))   :: r(true.B)   :: HNil
+    )),
 
-    (sh    , (r(false.B)    :: l(WriteSelect)::
+    (sh    , (
+      r(false.B)    :: l(WriteSelect)::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmS) :: l(Bool()) ::
-              r(true.B)     :: r(3.U(4.W))   :: r(true.B)   :: HNil)),
+      r(true.B)     :: r(3.U(4.W))   :: r(true.B)   :: HNil
+    )),
 
-    (sw    , (r(false.B)    :: l(WriteSelect)::
+    (sw    , (
+      r(false.B)    :: l(WriteSelect)::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAdd)     :: r(aSrcARs1)   :: r(aSrcBImmS) :: l(Bool()) ::
-              r(true.B)     :: r(15.U(4.W))  :: r(true.B)   :: HNil)),
+      r(true.B)     :: r(15.U(4.W))  :: r(true.B)   :: HNil
+    )),
 
     // ---- Integer Computational Instructions ---
 
-    (addi  , (r(true.B)     :: r(rAluOut)  ::
+    (addi  , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAdd)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-              r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)    :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (slti  , (r(true.B)     :: r(rAluOut)  ::
+    (slti  , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpSlt)     :: r(aSrcARs1) :: r(aSrcBImmI) :: r(true.B)  ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (sltiu , (r(true.B)     :: r(rAluOut)  ::
+    (sltiu , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpSltu)     :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (xori  , (r(true.B)     :: r(rAluOut)  ::
+    (xori  , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpXor)      :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (ori   , (r(true.B)     :: r(rAluOut)  ::
+    (ori   , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpOr)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (andi  , (r(true.B)     :: r(rAluOut)  ::
+    (andi  , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAnd)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (slli  , (r(true.B)     :: r(rAluOut)  ::
+    (slli  , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpSll)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (srli  , (r(true.B)     :: r(rAluOut)  ::
+    (srli  , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpSrl)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (srai  , (r(true.B)     :: r(rAluOut)  ::
+    (srai  , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpSra)     :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (add   , (r(true.B)     :: r(rAluOut)  ::
+    (add   , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAdd)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (sub   , (r(true.B)     :: r(rAluOut)  ::
+    (sub   , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpSub)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (sll   , (r(true.B)     :: r(rAluOut)  ::
+    (sll   , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpSll)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (slt   , (r(true.B)     :: r(rAluOut)  ::
+    (slt   , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpSlt)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: r(true.B)  ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (sltu  , (r(true.B)     :: r(rAluOut)  ::
+    (sltu  , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpSltu)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: r(false.B) ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (xor   , (r(true.B)     :: r(rAluOut)  ::
+    (xor   , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpXor)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (srl   , (r(true.B)     :: r(rAluOut)  ::
+    (srl   , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpSrl)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (sra   , (r(true.B)     :: r(rAluOut)  ::
+    (sra   , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpSra)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (or    , (r(true.B)     :: r(rAluOut)  ::
+    (or    , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpOr)      :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
 
-    (and   , (r(true.B)     :: r(rAluOut)  ::
+    (and   , (
+      r(true.B)     :: r(rAluOut)  ::
       r(false.B)    :: r(pStaticNpc) ::
       r(aOpAnd)     :: r(aSrcARs1) :: r(aSrcBRs2)  :: l(Bool())    ::
-              r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil)),
+      r(false.B)     :: l(UInt(4.W)):: r(false.B)   :: HNil
+    )),
   )
+  // format: on
 
   val default = BitPat(0.U(controlWidth.W))
 
 //   println(s"ControlMapping = ${ControlMapping.map(it => (it._1 -> toBits(it._2))).foreach(x => println(x._2))}\n")
   val out = decoder(
     inst,
-    TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default))
+    TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default)
+  )
   val srcList = slices.map(s => out(s._1, s._2))
 
   assert(out != default)
@@ -363,7 +447,13 @@ class Flow extends Module {
   val npc = Wire(dataType)
   npc := pc.out + 4.U
   pc.in.exeOut := alu.out.result
-  pc.in.immB := Cat(Fill(20, inst(31)), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W))
+  pc.in.immB := Cat(
+    Fill(20, inst(31)),
+    inst(7),
+    inst(30, 25),
+    inst(11, 8),
+    0.U(1.W)
+  )
 
   control.inst := inst
   reg.control <> control.reg
@@ -387,7 +477,8 @@ class Flow extends Module {
     Fill(8, ram.io.writeMask(3)),
     Fill(8, ram.io.writeMask(2)),
     Fill(8, ram.io.writeMask(1)),
-    "b11111111".U)
+    "b11111111".U
+  )
 
   val doSignExt = control.ram.writeMask(0)
   val signExt16 = control.ram.writeMask(1)
@@ -395,10 +486,14 @@ class Flow extends Module {
     reg.in.writeData(lit(rMemOut)) := maskedData
     // printf(cf"!doSignExt\n")
   }.elsewhen(signExt16) {
-    reg.in.writeData(lit(rMemOut)) := Cat(Fill(16, maskedData(15)), maskedData(15, 0))
+    reg.in.writeData(lit(rMemOut)) := Cat(
+      Fill(16, maskedData(15)),
+      maskedData(15, 0)
+    )
     // printf(cf"elsewhen\n")
   }.otherwise {
-    reg.in.writeData(lit(rMemOut)) := Cat(Fill(24, maskedData(7)), maskedData(7, 0))
+    reg.in
+      .writeData(lit(rMemOut)) := Cat(Fill(24, maskedData(7)), maskedData(7, 0))
     // printf(cf"otherwise\n")
   }
   // printf(cf"maskedData = ${maskedData}, writeData = ${reg.in.writeData(lit(rMemOut))}\n")
@@ -427,8 +522,21 @@ class Flow extends Module {
   alu.in.b(lit(aSrcBRs2)) := reg.out.src(1)
   // alu.in.b(lit(aSrcBImmI)) := inst(31, 20).pad(aSrcBImmI.getWidth)
   alu.in.b(lit(aSrcBImmI)) := Cat(Fill(20, inst(31)), inst(31, 20))
-  alu.in.b(lit(aSrcBImmJ)) := Cat(Fill(12, inst(31)), inst(19, 12), inst(20), inst(30, 25), inst(24, 21), 0.U(1.W))
+  alu.in.b(lit(aSrcBImmJ)) := Cat(
-  alu.in.b(lit(aSrcBImmS)) := Cat(Fill(20, inst(31)), inst(31), inst(30, 25), inst(11, 8), inst(7))
+    Fill(12, inst(31)),
+    inst(19, 12),
+    inst(20),
+    inst(30, 25),
+    inst(24, 21),
+    0.U(1.W)
+  )
+  alu.in.b(lit(aSrcBImmS)) := Cat(
+    Fill(20, inst(31)),
+    inst(31),
+    inst(30, 25),
+    inst(11, 8),
+    inst(7)
+  )
   alu.in.b(lit(aSrcBImmU)) := Cat(inst(31, 12), 0.U(12.W))
 
   Trace.traceName(pc.out)

npc/core/src/main/scala/top/Main.scala

@@ -13,7 +13,6 @@ import java.io.PrintWriter
 import scala.io.Source
 import java.io.File
 
-
 // TODO: Generate verilator config file
 
 object VerilogMain extends App {
@@ -34,35 +33,47 @@ object VerilogMain extends App {
   }
 
   val annos = (new ChiselStage).execute(
-    Array("--target-dir", opt.targetDir.toString, "--target", "systemverilog", "--split-verilog", "--full-stacktrace"),
+    Array(
+      "--target-dir",
+      opt.targetDir.toString,
+      "--target",
+      "systemverilog",
+      "--split-verilog",
+      "--full-stacktrace"
+    ),
     Seq(
-
+    ) ++ (if (config.traceConfig.enable)
-    ) ++ (if(config.traceConfig.enable) Seq(ChiselGeneratorAnnotation(() => new Flow)) else Seq())
+            Seq(ChiselGeneratorAnnotation(() => new Flow))
+          else Seq())
   )
 
-  if(config.traceConfig.enable) {
+  if (config.traceConfig.enable) {
-    val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[Flow]
+    val dut = annos
+      .collectFirst { case DesignAnnotation(dut) => dut }
+      .get
+      .asInstanceOf[Flow]
 
-    val verilatorConfigSeq = finalTargetMap(annos)
+    val verilatorConfigSeq = finalTargetMap(annos).values.flatten
-      .values
-      .flatten
       .map(ct =>
-        s"""public_flat_rd -module "${
+        s"""public_flat_rd -module "${ct.tokens.collectFirst {
-          ct.tokens.collectFirst { case OfModule(m) => m }.get
+            case OfModule(m) => m
-        }" -var "${ct.tokens.collectFirst { case Ref(r) => r }.get}"""")
+          }.get}" -var "${ct.tokens.collectFirst { case Ref(r) => r }.get}""""
-    finalTargetMap(annos)
+      )
-      .values
+    finalTargetMap(annos).values.flatten
-      .flatten
+      .foreach(ct =>
-      .foreach(
+        println(s"""TOP.${ct.circuit}.${ct.path
-        ct => println(s"""TOP.${ct.circuit}.${ct.path.map { case (Instance(i), _) => i }.mkString(".")}.${ct.tokens.collectFirst {
+            .map { case (Instance(i), _) => i }
-          case Ref(r) => r
+            .mkString(".")}.${ct.tokens.collectFirst { case Ref(r) =>
+            r
           }.get}""")
       )
 
-    val verilatorConfigWriter = new PrintWriter(new File(opt.targetDir, opt.verilatorConfigFileOut.toString()))
+    val verilatorConfigWriter = new PrintWriter(
+      new File(opt.targetDir, opt.verilatorConfigFileOut.toString())
+    )
     verilatorConfigWriter.write("`verilator_config\n")
     try {
-      for(ct <- verilatorConfigSeq) {
+      for (ct <- verilatorConfigSeq) {
         verilatorConfigWriter.println(ct)
       }
     } finally {

npc/core/src/main/scala/utils/Keyboard.scala

@@ -55,7 +55,7 @@ class KeyboardController extends Module {
 }
 
 class KeyboardSegController extends Module {
-  val io = IO(new Bundle{
+  val io = IO(new Bundle {
     val keycode = Flipped(Decoupled(UInt(8.W)))
     val segs = Vec(8, UInt(8.W))
   })
@@ -66,30 +66,60 @@ class KeyboardSegController extends Module {
 
   // 0x1C.U -> 0x41.U, ...
   val keycode_to_ascii = Seq(
-    0x1C.U, 0x32.U, 0x21.U, 0x23.U, 0x24.U, 0x2B.U,
+    0x1c.U,
-    0x34.U, 0x33.U, 0x43.U, 0x3B.U, 0x42.U, 0x4B.U,
+    0x32.U,
-    0x3A.U, 0x31.U, 0x44.U, 0x4D.U, 0x15.U, 0x2D.U,
+    0x21.U,
-    0x1B.U, 0x2C.U, 0x3C.U, 0x2A.U, 0x1D.U, 0x22.U,
+    0x23.U,
-    0x35.U, 0x1A.U, 0x45.U, 0x16.U, 0x1E.U, 0x26.U,
+    0x24.U,
-    0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
+    0x2b.U,
-  ).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
+    0x34.U,
+    0x33.U,
+    0x43.U,
+    0x3b.U,
+    0x42.U,
+    0x4b.U,
+    0x3a.U,
+    0x31.U,
+    0x44.U,
+    0x4d.U,
+    0x15.U,
+    0x2d.U,
+    0x1b.U,
+    0x2c.U,
+    0x3c.U,
+    0x2a.U,
+    0x1d.U,
+    0x22.U,
+    0x35.U,
+    0x1a.U,
+    0x45.U,
+    0x16.U,
+    0x1e.U,
+    0x26.U,
+    0x25.U,
+    0x2e.U,
+    0x36.U,
+    0x3d.U,
+    0x3e.U,
+    0x46.U
+  ).zip(((0x41 to 0x5a) ++ (0x30 to 0x39)).map(_.U))
 
   val keycode = RegInit(0.U(8.W))
-  val counter = Counter(0xFF)
+  val counter = Counter(0xff)
   val release_state = RegInit(Bool(), false.B)
   when(io.keycode.ready && io.keycode.valid) {
-    when(io.keycode.bits === 0xF0.U) {
+    when(io.keycode.bits === 0xf0.U) {
       release_state := true.B
     }.elsewhen(!release_state) {
       counter.inc()
       keycode := io.keycode.bits
-    }.otherwise{
+    }.otherwise {
       // Release code on io.keycode.bits
       release_state := false.B
     }
   }
 
-  val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
+  val keycode_digits = VecInit(keycode(3, 0)) ++ VecInit(keycode(7, 4))
   val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
 
   val seg_contoller = Module(new SegControllerGenerator(8, UInt(8.W)))

npc/core/src/main/scala/utils/SegControllerGenerator.scala

@@ -9,16 +9,32 @@ class SegControllerGenerator[T <: Data](seg_count: Int, t: T) extends Module {
     val in_segs = Input(Vec(seg_count / ((t.getWidth + 3) / 4), t))
     val segs = Output(Vec(seg_count, UInt(8.W)))
   })
-  val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq(
+  val digit_to_seg = ((0 until 16)
-    "b00000011".U, "b10011111".U, "b00100101".U, "b00001101".U,
+    .map(_.U))
-    "b10011001".U, "b01001001".U, "b01000001".U, "b00011111".U,
+    .zip(
-    "b00000001".U, "b00001001".U, "b00010001".U, "b11000001".U,
+      Seq(
-    "b01100011".U, "b10000101".U, "b01100001".U, "b01110001".U,
+        "b00000011".U,
-  ))
+        "b10011111".U,
+        "b00100101".U,
+        "b00001101".U,
+        "b10011001".U,
+        "b01001001".U,
+        "b01000001".U,
+        "b00011111".U,
+        "b00000001".U,
+        "b00001001".U,
+        "b00010001".U,
+        "b11000001".U,
+        "b01100011".U,
+        "b10000101".U,
+        "b01100001".U,
+        "b01110001".U
+      )
+    )
   val vec = io.in_segs.asTypeOf(Vec(seg_count, UInt(4.W)))
 
   val segs = VecInit(Seq.fill(seg_count)(0.U(8.W)))
-  segs := vec.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
+  segs := vec.map(MuxLookup(_, 0xff.U)(digit_to_seg))
 
   io.segs := segs
 }

npc/core/src/test/scala/CSR.scala

@@ -0,0 +1,59 @@
+package flow.tests
+
+import chisel3._
+import chiseltest._
+import org.scalatest.freespec.AnyFreeSpec
+import chiseltest.simulator.WriteVcdAnnotation
+
+import flow.components.CSRCore
+import flow.tests.defaultParams
+
+class CSRSpec extends AnyFreeSpec with ChiselScalatestTester {
+  implicit val p: flow.Params = defaultParams()
+  "should compile" in {
+    test(new CSRCore) { c =>
+      c.clock.step(1)
+    }
+  }
+  "Write" - {
+    "delayed" in {
+      test(new CSRCore) { c =>
+        val tv = BigInt("deadbeef", 16)
+        c.in.csrAddr.poke(c.nameToAddr("mstatus"))
+        c.in.writeData.poke(tv)
+        c.control.writeEnable.poke(c.control.csrWrite.csrWriteEnabled)
+        c.clock.step(1)
+
+        c.control.readEnable.poke(c.control.csrRead.csrReadEnabled)
+        c.out.readData.expect(0)
+        c.out.readValid.expect(1)
+
+        c.clock.step(1)
+        c.out.readValid.expect(1)
+        c.out.readData.expect(tv)
+      }
+    }
+  }
+
+  "Read" - {
+    "controlled by readEnable" in {
+      test(new CSRCore) { c =>
+        val tv = BigInt("deadbeef", 16)
+        c.in.csrAddr.poke(c.nameToAddr("mstatus"))
+        c.in.writeData.poke(tv)
+        c.control.readEnable.poke(c.control.csrRead.csrReadEnabled)
+        c.control.writeEnable.poke(c.control.csrWrite.csrWriteEnabled)
+        c.clock.step(1)
+
+        c.control.readEnable.poke(c.control.csrRead.csrReadDisabled)
+        c.out.readData.expect(0)
+        c.out.readValid.expect(0)
+
+        c.clock.step(1)
+        c.out.readData.expect(0)
+        c.out.readValid.expect(0)
+      }
+    }
+  }
+
+}

npc/core/src/test/scala/params.scala

@@ -0,0 +1,8 @@
+package flow.tests
+
+import chisel3._
+import flow.Params
+
+object defaultParams {
+  def apply(): Params = new Params(XLEN = 32.W)
+}