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2 commits
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8ee1551dc2
Author | SHA1 | Date | |
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8ee1551dc2 | |||
96ae890632 |
11 changed files with 88 additions and 105 deletions
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@ -1 +0,0 @@
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Subproject commit 8c4ea046225e2dce599dc36aeef6c4c857996d00
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1
diffu
1
diffu
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@ -1 +0,0 @@
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||||||
Subproject commit 645b0f607ae510fda4d71b8152ea932a2b38bc32
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11
flake.nix
11
flake.nix
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@ -11,6 +11,8 @@
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||||||
url = "git+https://git.xinyang.life/xin/nur.git";
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url = "git+https://git.xinyang.life/xin/nur.git";
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||||||
inputs.nixpkgs.follows = "nixpkgs";
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inputs.nixpkgs.follows = "nixpkgs";
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};
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};
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# diffu.url = "github:xinyangli/diffu";
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# am-kernels.url = "git+https://git.xinyang.life/xin/am-kernels.git";
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};
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};
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outputs = { self, flake-utils, nixpkgs, nixpkgs-circt162, pre-commit-hooks, nur-xin }@inputs:
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outputs = { self, flake-utils, nixpkgs, nixpkgs-circt162, pre-commit-hooks, nur-xin }@inputs:
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@ -65,13 +67,9 @@
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abstract-machine = pkgs.callPackage ./abstract-machine { isa = "native"; };
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abstract-machine = pkgs.callPackage ./abstract-machine { isa = "native"; };
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nemu = pkgs.callPackage ./nemu { };
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nemu = pkgs.callPackage ./nemu { };
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nemu-lib = pkgs.callPackage ./nemu { };
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nemu-lib = pkgs.callPackage ./nemu { };
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am-kernels = pkgs.callPackage ./am-kernels { abstract-machine = abstract-machine; arch = "native"; };
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rv32Cross = rec {
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rv32Cross = rec {
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abstract-machine = rv32CrossConfig.callPackage ./abstract-machine { isa = "riscv"; platform = [ "nemu" "npc" ]; };
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abstract-machine = rv32CrossConfig.callPackage ./abstract-machine { isa = "riscv"; platform = [ "nemu" "npc" ]; };
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am-kernels-npc = rv32CrossConfig.callPackage ./am-kernels { inherit abstract-machine; arch = "riscv-npc"; };
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am-kernels-nemu = rv32CrossConfig.callPackage ./am-kernels { inherit abstract-machine; arch = "riscv-nemu"; };
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am-kernels = rv32CrossConfig.callPackage ./am-kernels { abstract-machine = abstract-machine; arch = "riscv"; };
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};
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};
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};
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};
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@ -94,13 +92,13 @@
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self.packages.${system}.nemu
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self.packages.${system}.nemu
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];
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];
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NEMU_HOME = "/home/xin/repo/ysyx-workbench/nemu";
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NEMU_HOME = "/home/xin/repo/ysyx-workbench/nemu";
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NEMU_IMAGES_PATH = self.packages.${system}.rv32Cross.am-kernels-nemu + "/share/am-kernels";
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# NEMU_IMAGES_PATH = self.packages.${system}.rv32Cross.am-kernels-nemu + "/share/am-kernels";
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};
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};
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devShells.npc = pkgs.mkShell.override { stdenv = pkgs.ccacheStdenv; } {
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devShells.npc = pkgs.mkShell.override { stdenv = pkgs.ccacheStdenv; } {
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inherit (self.checks.${system}.pre-commit-check) shellHook;
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inherit (self.checks.${system}.pre-commit-check) shellHook;
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CHISEL_FIRTOOL_PATH = "${nixpkgs-circt162.legacyPackages.${system}.circt}/bin";
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CHISEL_FIRTOOL_PATH = "${nixpkgs-circt162.legacyPackages.${system}.circt}/bin";
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NPC_IMAGES_PATH = "${self.packages.${system}.rv32Cross.am-kernels-npc}/share/am-kernels";
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# NPC_IMAGES_PATH = "${self.packages.${system}.rv32Cross.am-kernels-npc}/share/am-kernels";
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packages = with pkgs; [
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packages = with pkgs; [
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clang-tools
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clang-tools
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cmake
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cmake
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@ -125,7 +123,6 @@
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flex
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flex
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||||||
bison
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bison
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verilator
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verilator
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self.packages.${system}.rv32Cross.am-kernels-npc
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];
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];
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buildInputs = with pkgs; [
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buildInputs = with pkgs; [
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@ -1,5 +1,4 @@
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||||||
menuconfig DEVICE
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menuconfig DEVICE
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depends on !TARGET_SHARE
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bool "Devices"
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bool "Devices"
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default n
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default n
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help
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help
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||||||
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@ -13,17 +13,17 @@
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* See the Mulan PSL v2 for more details.
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* See the Mulan PSL v2 for more details.
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||||||
***************************************************************************************/
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***************************************************************************************/
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||||||
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#include <device/map.h>
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#include <isa.h>
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#include <isa.h>
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#include <memory/host.h>
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#include <memory/host.h>
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#include <memory/vaddr.h>
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#include <memory/vaddr.h>
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#include <device/map.h>
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#define IO_SPACE_MAX (2 * 1024 * 1024)
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#define IO_SPACE_MAX (2 * 1024 * 1024)
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static uint8_t *io_space = NULL;
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static uint8_t *io_space = NULL;
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static uint8_t *p_space = NULL;
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static uint8_t *p_space = NULL;
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||||||
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||||||
uint8_t* new_space(int size) {
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uint8_t *new_space(int size) {
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uint8_t *p = p_space;
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uint8_t *p = p_space;
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// page aligned;
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// page aligned;
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size = (size + (PAGE_SIZE - 1)) & ~PAGE_MASK;
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size = (size + (PAGE_SIZE - 1)) & ~PAGE_MASK;
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||||||
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@ -33,17 +33,25 @@ uint8_t* new_space(int size) {
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}
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}
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static void check_bound(IOMap *map, paddr_t addr) {
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static void check_bound(IOMap *map, paddr_t addr) {
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#ifndef CONFIG_TARGET_SHARE
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if (map == NULL) {
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if (map == NULL) {
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Assert(map != NULL, "address (" FMT_PADDR ") is out of bound at pc = " FMT_WORD, addr, cpu.pc);
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Assert(map != NULL,
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"address (" FMT_PADDR ") is out of bound at pc = " FMT_WORD, addr,
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cpu.pc);
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} else {
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} else {
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||||||
Assert(addr <= map->high && addr >= map->low,
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Assert(addr <= map->high && addr >= map->low,
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||||||
"address (" FMT_PADDR ") is out of bound {%s} [" FMT_PADDR ", " FMT_PADDR "] at pc = " FMT_WORD,
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"address (" FMT_PADDR ") is out of bound {%s} [" FMT_PADDR
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||||||
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", " FMT_PADDR "] at pc = " FMT_WORD,
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||||||
addr, map->name, map->low, map->high, cpu.pc);
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addr, map->name, map->low, map->high, cpu.pc);
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||||||
}
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}
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||||||
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#endif
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||||||
}
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}
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||||||
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||||||
static void invoke_callback(io_callback_t c, paddr_t offset, int len, bool is_write) {
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static void invoke_callback(io_callback_t c, paddr_t offset, int len,
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if (c != NULL) { c(offset, len, is_write); }
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bool is_write) {
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||||||
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if (c != NULL) {
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||||||
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c(offset, len, is_write);
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||||||
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}
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||||||
}
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}
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||||||
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||||||
void init_map() {
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void init_map() {
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||||||
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|
@ -86,38 +86,16 @@ static void decode_operand(Decode *s, int *rd, word_t *src1, word_t *src2,
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int rs2 = BITS(i, 24, 20);
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int rs2 = BITS(i, 24, 20);
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*rd = BITS(i, 11, 7);
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*rd = BITS(i, 11, 7);
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switch (type) {
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switch (type) {
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case TYPE_R:
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// clang-format off
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||||||
src1R();
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case TYPE_R: src1R(); src2R(); break;
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src2R();
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case TYPE_I: src1R(); immI(); break;
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||||||
break;
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case TYPE_U: immU(); break;
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||||||
case TYPE_I:
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case TYPE_J: immJ(); break;
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||||||
src1R();
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case TYPE_S: src1R(); src2R(); immS(); break;
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||||||
immI();
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case TYPE_B: src1R(); src2R(); immB(); break;
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||||||
break;
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case TYPE_CSR: src1R(); csr(); break;
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case TYPE_U:
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case TYPE_CSRI: csr(); uimm(); break;
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immU();
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// clang-format on
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break;
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case TYPE_J:
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immJ();
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break;
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case TYPE_S:
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src1R();
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||||||
src2R();
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immS();
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||||||
break;
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||||||
case TYPE_B:
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||||||
src1R();
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||||||
src2R();
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||||||
immB();
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||||||
break;
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||||||
case TYPE_CSR:
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||||||
src1R();
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||||||
csr();
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||||||
break;
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||||||
case TYPE_CSRI:
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||||||
csr();
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||||||
uimm();
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||||||
break;
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||||||
}
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}
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||||||
}
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}
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||||||
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||||||
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@ -271,6 +249,9 @@ static int decode_exec(Decode *s) {
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||||||
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||||||
// "Previledge"
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// "Previledge"
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||||||
// -- CSR instructions
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// -- CSR instructions
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||||||
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// src2: R(read register)
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||||||
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// src1: R(write source)
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||||||
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// imm: write data()
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||||||
INSTPAT(
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INSTPAT(
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||||||
"??????? ????? ????? 001 ????? 11100 11", csrrw, CSR, do {
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"??????? ????? ????? 001 ????? 11100 11", csrrw, CSR, do {
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||||||
R(rd) = read_csr(cpu.csr, src2);
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R(rd) = read_csr(cpu.csr, src2);
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||||||
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@ -52,13 +52,11 @@ word_t isa_reg_str2val(const char *s, bool *success) {
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||||||
}
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}
|
||||||
|
|
||||||
int isa_read_reg(void *args, int regno, size_t *reg_value) {
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int isa_read_reg(void *args, int regno, size_t *reg_value) {
|
||||||
if (regno > 33) {
|
if (regno > 32) {
|
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return EFAULT;
|
return EFAULT;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (regno == 33) {
|
if (regno == 32) {
|
||||||
*reg_value = cpu.csr[MTVEC];
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|
||||||
} else if (regno == 32) {
|
|
||||||
*reg_value = cpu.pc;
|
*reg_value = cpu.pc;
|
||||||
} else {
|
} else {
|
||||||
*reg_value = cpu.gpr[regno];
|
*reg_value = cpu.gpr[regno];
|
||||||
|
@ -67,13 +65,11 @@ int isa_read_reg(void *args, int regno, size_t *reg_value) {
|
||||||
}
|
}
|
||||||
|
|
||||||
int isa_write_reg(void *args, int regno, size_t data) {
|
int isa_write_reg(void *args, int regno, size_t data) {
|
||||||
if (regno > 33) {
|
if (regno > 32) {
|
||||||
return EFAULT;
|
return EFAULT;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (regno == 33) {
|
if (regno == 32) {
|
||||||
cpu.csr[MTVEC] = data;
|
|
||||||
} else if (regno == 32) {
|
|
||||||
cpu.pc = data;
|
cpu.pc = data;
|
||||||
} else {
|
} else {
|
||||||
cpu.gpr[regno] = data;
|
cpu.gpr[regno] = data;
|
||||||
|
@ -81,6 +77,6 @@ int isa_write_reg(void *args, int regno, size_t data) {
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
__EXPORT arch_info_t isa_arch_info = {.reg_num = 33,
|
__EXPORT arch_info_t isa_arch_info = {.reg_num = 32,
|
||||||
.reg_byte = MUXDEF(CONFIG_RV64, 8, 4),
|
.reg_byte = MUXDEF(CONFIG_RV64, 8, 4),
|
||||||
.target_desc = TARGET_RV32};
|
.target_desc = TARGET_RV32};
|
||||||
|
|
|
@ -15,6 +15,7 @@
|
||||||
|
|
||||||
#include "common.h"
|
#include "common.h"
|
||||||
#include "debug.h"
|
#include "debug.h"
|
||||||
|
#include "utils.h"
|
||||||
#include <device/mmio.h>
|
#include <device/mmio.h>
|
||||||
#include <isa.h>
|
#include <isa.h>
|
||||||
#include <memory/host.h>
|
#include <memory/host.h>
|
||||||
|
@ -44,9 +45,14 @@ static void pmem_write(paddr_t addr, int len, word_t data) {
|
||||||
}
|
}
|
||||||
|
|
||||||
static void out_of_bound(paddr_t addr) {
|
static void out_of_bound(paddr_t addr) {
|
||||||
|
#ifdef CONFIG_TARGET_SHARE
|
||||||
|
// Do not panic when used as a library. Give an error in log
|
||||||
|
Error("Out of bound at 0x%x", addr);
|
||||||
|
#else
|
||||||
panic("address = " FMT_PADDR " is out of bound of pmem [" FMT_PADDR
|
panic("address = " FMT_PADDR " is out of bound of pmem [" FMT_PADDR
|
||||||
", " FMT_PADDR "] at pc = " FMT_WORD,
|
", " FMT_PADDR "] at pc = " FMT_WORD,
|
||||||
addr, PMEM_LEFT, PMEM_RIGHT, cpu.pc);
|
addr, PMEM_LEFT, PMEM_RIGHT, cpu.pc);
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_MTRACE
|
#ifdef CONFIG_MTRACE
|
||||||
|
|
|
@ -1,3 +1,4 @@
|
||||||
|
#include "types.h"
|
||||||
#include "utils.h"
|
#include "utils.h"
|
||||||
#include <vector>
|
#include <vector>
|
||||||
|
|
||||||
|
@ -18,7 +19,7 @@ typedef struct {
|
||||||
|
|
||||||
__EXPORT size_t nemu_dbg_state_size = sizeof(DbgState);
|
__EXPORT size_t nemu_dbg_state_size = sizeof(DbgState);
|
||||||
__EXPORT bool nemu_do_difftest = true;
|
__EXPORT bool nemu_do_difftest = true;
|
||||||
__EXPORT arch_info_t nemu_isa_arch_info;
|
__EXPORT arch_info_t nemu_isa_arch_info = isa_arch_info;
|
||||||
|
|
||||||
__EXPORT int nemu_read_mem(void *args, size_t addr, size_t len, void *val) {
|
__EXPORT int nemu_read_mem(void *args, size_t addr, size_t len, void *val) {
|
||||||
if (!in_pmem(addr))
|
if (!in_pmem(addr))
|
||||||
|
|
|
@ -59,7 +59,8 @@ extern "C" void init_disasm(const char *triple) {
|
||||||
llvm::MCRegisterInfo *gMRI = nullptr;
|
llvm::MCRegisterInfo *gMRI = nullptr;
|
||||||
auto target = llvm::TargetRegistry::lookupTarget(gTriple, errstr);
|
auto target = llvm::TargetRegistry::lookupTarget(gTriple, errstr);
|
||||||
if (!target) {
|
if (!target) {
|
||||||
llvm::errs() << "Can't find target for " << gTriple << ": " << errstr << "\n";
|
llvm::errs() << "Can't find target for " << gTriple << ": " << errstr
|
||||||
|
<< "\n";
|
||||||
assert(0);
|
assert(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -79,20 +80,22 @@ extern "C" void init_disasm(const char *triple) {
|
||||||
#if LLVM_VERSION_MAJOR >= 13
|
#if LLVM_VERSION_MAJOR >= 13
|
||||||
auto llvmTripleTwine = Twine(triple);
|
auto llvmTripleTwine = Twine(triple);
|
||||||
auto llvmtriple = llvm::Triple(llvmTripleTwine);
|
auto llvmtriple = llvm::Triple(llvmTripleTwine);
|
||||||
auto Ctx = new llvm::MCContext(llvmtriple,AsmInfo, gMRI, nullptr);
|
auto Ctx = new llvm::MCContext(llvmtriple, AsmInfo, gMRI, nullptr);
|
||||||
#else
|
#else
|
||||||
auto Ctx = new llvm::MCContext(AsmInfo, gMRI, nullptr);
|
auto Ctx = new llvm::MCContext(AsmInfo, gMRI, nullptr);
|
||||||
#endif
|
#endif
|
||||||
gDisassembler = target->createMCDisassembler(*gSTI, *Ctx);
|
gDisassembler = target->createMCDisassembler(*gSTI, *Ctx);
|
||||||
gIP = target->createMCInstPrinter(llvm::Triple(gTriple),
|
gIP = target->createMCInstPrinter(llvm::Triple(gTriple),
|
||||||
AsmInfo->getAssemblerDialect(), *AsmInfo, *gMII, *gMRI);
|
AsmInfo->getAssemblerDialect(), *AsmInfo,
|
||||||
|
*gMII, *gMRI);
|
||||||
gIP->setPrintImmHex(true);
|
gIP->setPrintImmHex(true);
|
||||||
gIP->setPrintBranchImmAsAddress(true);
|
gIP->setPrintBranchImmAsAddress(true);
|
||||||
if (isa == "riscv32" || isa == "riscv64")
|
if (isa == "riscv32" || isa == "riscv64")
|
||||||
gIP->applyTargetSpecificCLOption("no-aliases");
|
gIP->applyTargetSpecificCLOption("no-aliases");
|
||||||
}
|
}
|
||||||
|
|
||||||
extern "C" void disassemble(char *str, int size, uint64_t pc, uint8_t *code, int nbyte) {
|
extern "C" void disassemble(char *str, int size, uint64_t pc, uint8_t *code,
|
||||||
|
int nbyte) {
|
||||||
MCInst inst;
|
MCInst inst;
|
||||||
llvm::ArrayRef<uint8_t> arr(code, nbyte);
|
llvm::ArrayRef<uint8_t> arr(code, nbyte);
|
||||||
uint64_t dummy_size = 0;
|
uint64_t dummy_size = 0;
|
||||||
|
|
|
@ -13,17 +13,18 @@
|
||||||
* See the Mulan PSL v2 for more details.
|
* See the Mulan PSL v2 for more details.
|
||||||
***************************************************************************************/
|
***************************************************************************************/
|
||||||
|
|
||||||
|
#include "../../include/common.h"
|
||||||
#include "mmu.h"
|
#include "mmu.h"
|
||||||
#include "sim.h"
|
#include "sim.h"
|
||||||
#include "../../include/common.h"
|
|
||||||
#include <difftest-def.h>
|
#include <difftest-def.h>
|
||||||
|
|
||||||
#define NR_GPR MUXDEF(CONFIG_RVE, 16, 32)
|
#define NR_GPR MUXDEF(CONFIG_RVE, 16, 32)
|
||||||
|
|
||||||
static std::vector<std::pair<reg_t, abstract_device_t*>> difftest_plugin_devices;
|
static std::vector<std::pair<reg_t, abstract_device_t *>>
|
||||||
|
difftest_plugin_devices;
|
||||||
static std::vector<std::string> difftest_htif_args;
|
static std::vector<std::string> difftest_htif_args;
|
||||||
static std::vector<std::pair<reg_t, mem_t*>> difftest_mem(
|
static std::vector<std::pair<reg_t, mem_t *>>
|
||||||
1, std::make_pair(reg_t(DRAM_BASE), new mem_t(CONFIG_MSIZE)));
|
difftest_mem(1, std::make_pair(reg_t(DRAM_BASE), new mem_t(CONFIG_MSIZE)));
|
||||||
static debug_module_config_t difftest_dm_config = {
|
static debug_module_config_t difftest_dm_config = {
|
||||||
.progbufsize = 2,
|
.progbufsize = 2,
|
||||||
.max_sba_data_width = 0,
|
.max_sba_data_width = 0,
|
||||||
|
@ -33,15 +34,14 @@ static debug_module_config_t difftest_dm_config = {
|
||||||
.support_abstract_csr_access = true,
|
.support_abstract_csr_access = true,
|
||||||
.support_abstract_fpr_access = true,
|
.support_abstract_fpr_access = true,
|
||||||
.support_haltgroups = true,
|
.support_haltgroups = true,
|
||||||
.support_impebreak = true
|
.support_impebreak = true};
|
||||||
};
|
|
||||||
|
|
||||||
struct diff_context_t {
|
struct diff_context_t {
|
||||||
word_t gpr[MUXDEF(CONFIG_RVE, 16, 32)];
|
word_t gpr[MUXDEF(CONFIG_RVE, 16, 32)];
|
||||||
word_t pc;
|
word_t pc;
|
||||||
};
|
};
|
||||||
|
|
||||||
static sim_t* s = NULL;
|
static sim_t *s = NULL;
|
||||||
static processor_t *p = NULL;
|
static processor_t *p = NULL;
|
||||||
static state_t *state = NULL;
|
static state_t *state = NULL;
|
||||||
|
|
||||||
|
@ -50,36 +50,35 @@ void sim_t::diff_init(int port) {
|
||||||
state = p->get_state();
|
state = p->get_state();
|
||||||
}
|
}
|
||||||
|
|
||||||
void sim_t::diff_step(uint64_t n) {
|
void sim_t::diff_step(uint64_t n) { step(n); }
|
||||||
step(n);
|
|
||||||
}
|
|
||||||
|
|
||||||
void sim_t::diff_get_regs(void* diff_context) {
|
void sim_t::diff_get_regs(void *diff_context) {
|
||||||
struct diff_context_t* ctx = (struct diff_context_t*)diff_context;
|
struct diff_context_t *ctx = (struct diff_context_t *)diff_context;
|
||||||
for (int i = 0; i < NR_GPR; i++) {
|
for (int i = 0; i < NR_GPR; i++) {
|
||||||
ctx->gpr[i] = state->XPR[i];
|
ctx->gpr[i] = state->XPR[i];
|
||||||
}
|
}
|
||||||
ctx->pc = state->pc;
|
ctx->pc = state->pc;
|
||||||
}
|
}
|
||||||
|
|
||||||
void sim_t::diff_set_regs(void* diff_context) {
|
void sim_t::diff_set_regs(void *diff_context) {
|
||||||
struct diff_context_t* ctx = (struct diff_context_t*)diff_context;
|
struct diff_context_t *ctx = (struct diff_context_t *)diff_context;
|
||||||
for (int i = 0; i < NR_GPR; i++) {
|
for (int i = 0; i < NR_GPR; i++) {
|
||||||
state->XPR.write(i, (sword_t)ctx->gpr[i]);
|
state->XPR.write(i, (sword_t)ctx->gpr[i]);
|
||||||
}
|
}
|
||||||
state->pc = ctx->pc;
|
state->pc = ctx->pc;
|
||||||
}
|
}
|
||||||
|
|
||||||
void sim_t::diff_memcpy(reg_t dest, void* src, size_t n) {
|
void sim_t::diff_memcpy(reg_t dest, void *src, size_t n) {
|
||||||
mmu_t* mmu = p->get_mmu();
|
mmu_t *mmu = p->get_mmu();
|
||||||
for (size_t i = 0; i < n; i++) {
|
for (size_t i = 0; i < n; i++) {
|
||||||
mmu->store<uint8_t>(dest+i, *((uint8_t*)src+i));
|
mmu->store<uint8_t>(dest + i, *((uint8_t *)src + i));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
extern "C" {
|
extern "C" {
|
||||||
|
|
||||||
__EXPORT void difftest_memcpy(paddr_t addr, void *buf, size_t n, bool direction) {
|
__EXPORT void difftest_memcpy(paddr_t addr, void *buf, size_t n,
|
||||||
|
bool direction) {
|
||||||
if (direction == DIFFTEST_TO_REF) {
|
if (direction == DIFFTEST_TO_REF) {
|
||||||
s->diff_memcpy(addr, buf, n);
|
s->diff_memcpy(addr, buf, n);
|
||||||
} else {
|
} else {
|
||||||
|
@ -87,7 +86,7 @@ __EXPORT void difftest_memcpy(paddr_t addr, void *buf, size_t n, bool direction)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
__EXPORT void difftest_regcpy(void* dut, bool direction) {
|
__EXPORT void difftest_regcpy(void *dut, bool direction) {
|
||||||
if (direction == DIFFTEST_TO_REF) {
|
if (direction == DIFFTEST_TO_REF) {
|
||||||
s->diff_set_regs(dut);
|
s->diff_set_regs(dut);
|
||||||
} else {
|
} else {
|
||||||
|
@ -95,31 +94,27 @@ __EXPORT void difftest_regcpy(void* dut, bool direction) {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
__EXPORT void difftest_exec(uint64_t n) {
|
__EXPORT void difftest_exec(uint64_t n) { s->diff_step(n); }
|
||||||
s->diff_step(n);
|
|
||||||
}
|
|
||||||
|
|
||||||
__EXPORT void difftest_init(int port) {
|
__EXPORT void difftest_init(int port) {
|
||||||
difftest_htif_args.push_back("");
|
difftest_htif_args.push_back("");
|
||||||
const char *isa = "RV" MUXDEF(CONFIG_RV64, "64", "32") MUXDEF(CONFIG_RVE, "E", "I") "MAFDC";
|
const char *isa =
|
||||||
|
"RV" MUXDEF(CONFIG_RV64, "64", "32") MUXDEF(CONFIG_RVE, "E", "I") "MAFDC";
|
||||||
cfg_t cfg(/*default_initrd_bounds=*/std::make_pair((reg_t)0, (reg_t)0),
|
cfg_t cfg(/*default_initrd_bounds=*/std::make_pair((reg_t)0, (reg_t)0),
|
||||||
/*default_bootargs=*/nullptr,
|
/*default_bootargs=*/nullptr,
|
||||||
/*default_isa=*/isa,
|
/*default_isa=*/isa,
|
||||||
/*default_priv=*/DEFAULT_PRIV,
|
/*default_priv=*/DEFAULT_PRIV,
|
||||||
/*default_varch=*/DEFAULT_VARCH,
|
/*default_varch=*/DEFAULT_VARCH,
|
||||||
/*default_misaligned=*/false,
|
/*default_misaligned=*/false,
|
||||||
/*default_endianness*/endianness_little,
|
/*default_endianness*/ endianness_little,
|
||||||
/*default_pmpregions=*/16,
|
/*default_pmpregions=*/16,
|
||||||
/*default_mem_layout=*/std::vector<mem_cfg_t>(),
|
/*default_mem_layout=*/std::vector<mem_cfg_t>(),
|
||||||
/*default_hartids=*/std::vector<size_t>(1),
|
/*default_hartids=*/std::vector<size_t>(1),
|
||||||
/*default_real_time_clint=*/false,
|
/*default_real_time_clint=*/false,
|
||||||
/*default_trigger_count=*/4);
|
/*default_trigger_count=*/4);
|
||||||
s = new sim_t(&cfg, false,
|
s = new sim_t(&cfg, false, difftest_mem, difftest_plugin_devices,
|
||||||
difftest_mem, difftest_plugin_devices, difftest_htif_args,
|
difftest_htif_args, difftest_dm_config, nullptr, false, NULL,
|
||||||
difftest_dm_config, nullptr, false, NULL,
|
false, NULL, true);
|
||||||
false,
|
|
||||||
NULL,
|
|
||||||
true);
|
|
||||||
s->diff_init(port);
|
s->diff_init(port);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -127,5 +122,4 @@ __EXPORT void difftest_raise_intr(uint64_t NO) {
|
||||||
trap_t t(NO);
|
trap_t t(NO);
|
||||||
p->take_trap_public(t, state->pc);
|
p->take_trap_public(t, state->pc);
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue