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@ -1,7 +1,11 @@
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#include <array>
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#include <cstddef>
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#include <cstdint>
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#include <filesystem>
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#include <sys/types.h>
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#include <vpi_user.h>
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#include <VFlow.h>
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#include <cstdlib>
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#include <vector>
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#include <memory>
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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@ -10,77 +14,142 @@
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#define MAX_SIM_TIME 100
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#define VERILATOR_TRACE
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std::vector<vpiHandle> regsHandle;
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int regs[32];
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static void init_vpi_regs() {
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std::string regfile = "TOP.Flow.reg_0.regFile_";
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for(int i = 0; i < 32; i++) {
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std::string regname = regfile + std::to_string(i);
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vpiHandle vh = vpi_handle_by_name((PLI_BYTE8 *)regname.c_str(), NULL);
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regsHandle.push_back(vh);
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}
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}
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static void init_vpi() {
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init_vpi_regs();
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}
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static int vpi_get_int(vpiHandle vh) {
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s_vpi_value v;
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v.format = vpiIntVal;
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vpi_get_value(vh, &v);
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return v.value.integer;
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}
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static void update_regs() {
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for(int i = 0; i < 32; i++) {
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regs[i] = vpi_get_int(regsHandle[i]);
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}
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}
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static void print_regs() {
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for(int i = 0; i < 32; i++) {
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printf("%d: %d\t", i, regs[i]);
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if(i % 8 == 7) putchar('\n');
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}
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putchar('\n');
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}
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static int sim_time = 0;
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int main(int argc, char **argv, char **env) {
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int sim_time = 0;
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int posedge_cnt = 0;
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Verilated::commandArgs(argc, argv);
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std::unique_ptr<VFlow> top{new VFlow};
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Verilated::traceEverOn(true);
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VerilatedVcdC *m_trace = new VerilatedVcdC;
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template <class T>
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class Tracer {
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#ifdef VERILATOR_TRACE
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top->trace(m_trace, 5);
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m_trace->open("waveform.vcd");
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std::shared_ptr<T> top;
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std::unique_ptr<VerilatedVcdC> m_trace;
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uint64_t cycle = 0;
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#endif
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public:
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Tracer(T *top, std::filesystem::path wavefile) {
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#ifdef VERILATOR_TRACE
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top = top;
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Verilated::traceEverOn(true);
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m_trace = std::make_unique<VerilatedVcdC>();
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top->trace(m_trace.get(), 5);
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m_trace->open(wavefile.c_str());
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#endif
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}
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~Tracer() {
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#ifdef VERILATOR_TRACE
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m_trace->close();
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#endif
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init_vpi();
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top->reset = 0;
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for (sim_time = 10; sim_time < MAX_SIM_TIME; sim_time++) {
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top->eval();
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top->clock = !top->clock;
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if(top->clock == 1) {
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// Posedge
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++posedge_cnt;
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update_regs();
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print_regs();
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}
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/**
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* Dump signals to waveform file. Must be called once after every top->eval() call.
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*/
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void update() {
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#ifdef VERILATOR_TRACE
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m_trace->dump(sim_time);
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m_trace->dump(cycle++);
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#endif
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}
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};
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template <typename T, std::size_t nr>
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class _RegistersBase {
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std::array<T, nr> regs;
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virtual T fetch_reg(size_t id);
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public:
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void update() {
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for(int i = 0; i < regs.size(); i++) {
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regs[i] = fetch_reg(i);
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}
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}
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void print_regs() {
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for(int i = 0; i < regs.size(); i++) {
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printf("%d: %d\t", i, regs[i]);
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if(i % 8 == 7) putchar('\n');
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}
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putchar('\n');
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}
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};
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template <typename T, std::size_t nr>
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class _RegistersVPI : public _RegistersBase<T, nr> {
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std::array<vpiHandle, nr> reg_handles;
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T fetch_reg(size_t id) {
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s_vpi_value v;
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v.format = vpiIntVal;
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vpi_get_value(reg_handles[id], &v);
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return v.value.integer;
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}
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#ifdef VERILATOR_TRACE
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m_trace->close();
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#endif
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exit(EXIT_SUCCESS);
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public:
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_RegistersVPI<T, nr>(const std::string regs_prefix) {
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for(int i = 0; i < nr; i++) {
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std::string regname = regs_prefix + std::to_string(i);
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vpiHandle vh = vpi_handle_by_name((PLI_BYTE8 *)regname.c_str(), NULL);
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reg_handles[i] = vh;
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}
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}
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};
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typedef _RegistersVPI<uint32_t, 32> Registers;
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template <typename T, std::size_t n>
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class Memory {
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std::array<T, n> mem;
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size_t addr_to_index(size_t addr) {
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// Linear mapping
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return addr - 0x80000000;
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}
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public:
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const T& operator[](size_t addr) {
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return mem[addr_to_index(index)];
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}
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};
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template <typename T>
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class VlModuleInterfaceCommon : public T {
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uint64_t sim_time = 0;
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uint64_t posedge_cnt = 0;
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std::unique_ptr<Tracer<T>> tracer;
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public:
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VlModuleInterfaceCommon<T>(bool do_trace, std::filesystem::path wavefile = "waveform.vcd") {
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if(do_trace) tracer = std::make_unique<Tracer<T>>(this, wavefile);
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}
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void eval() {
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if(this->is_posedge()) {
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posedge_cnt++;
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}
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T::clock = !T::clock;
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sim_time++;
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T::eval();
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if(tracer) tracer->update();
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}
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void eval(int n) {
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for(int i = 0; i < n; i++) {
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this->eval();
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}
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}
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void reset_eval(int n) {
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this->reset = 1;
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this->eval(n);
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this->reset = 0;
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}
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bool is_posedge() {
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// Will be posedge when eval is called
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return T::clock == 0;
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}
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};
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typedef VlModuleInterfaceCommon<VFlow> VlModule;
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int main(int argc, char **argv, char **env) {
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Verilated::commandArgs(argc, argv);
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auto top = std::make_shared<VlModule>(false, "waveform.vcd");
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Registers regs("TOP.Flow.reg_0.regFile_");
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top->reset_eval(10);
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for (int i = 0; i < MAX_SIM_TIME; i++) {
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if(top->is_posedge()) {
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// Posedge
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regs.update();
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regs.print_regs();
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}
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top->eval();
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}
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return 0;
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}
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