Merge pull request 'npc: basic architecture implementation' (#2) from npc into master

Reviewed-on: #2

npc/CMakeLists.txt

@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.20)
 
-project(npc)
+project(flow)
 set (CMAKE_CXX_STANDARD 11)
 cmake_policy(SET CMP0144 NEW)
 
@@ -17,7 +17,7 @@ find_package(verilator REQUIRED)
 find_library(NVBOARD_LIBRARY NAMES nvboard)
 find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h)
 
-set(TOPMODULES "Switch" "Keyboard")
+set(TOPMODULES "Flow")
 
 foreach(TOPMODULE IN LISTS TOPMODULES)
  
@@ -58,7 +58,7 @@ foreach(TOPMODULE IN LISTS TOPMODULES)
   file(GLOB_RECURSE SOURCES csrc_nvboard/${TOPMODULE}/*.cpp)
   add_executable(V${TOPMODULE}_nvboard ${SOURCES} ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/auto_bind.cpp)
 
-  verilate(V${TOPMODULE}_nvboard TRACE COVERAGE THREADS
+  verilate(V${TOPMODULE}_nvboard TRACE THREADS
     TOP_MODULE ${TOPMODULE}
     PREFIX V${TOPMODULE}
     SOURCES ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc/${TOPMODULE}.v)

npc/constr/Flow.nxdc

@@ -0,0 +1,3 @@
+top=Flow
+
+io_clock(LD0)

npc/core/build.sbt

@@ -2,14 +2,14 @@ ThisBuild / scalaVersion     := "2.13.12"
 ThisBuild / version          := "0.1.0"
 
 
-val chiselVersion = "5.1.0"
+val chiselVersion = "6.2.0"
 
 lazy val root = (project in file("."))
   .settings(
     name := "flow",
     libraryDependencies ++= Seq(
       "org.chipsalliance" %% "chisel" % chiselVersion,
-      "edu.berkeley.cs" %% "chiseltest" % "5.0.2" % "test",
+      "edu.berkeley.cs" %% "chiseltest" % "6.0.0" % "test",
       "com.chuusai" %% "shapeless" % "2.3.3"
     ),
     scalacOptions ++= Seq(

npc/core/src/main/scala/ALU.scala

@@ -1,34 +1,63 @@
-package npc.util
+package flow.components
 
 import chisel3._
 import chisel3.util._
+import shapeless.{HNil, ::}
 
-class ALUGenerator(width: Int) extends Module {
+class ALUControlInterface extends Bundle {
-  require(width >= 0)
+  object OpSelect extends ChiselEnum {
-  val io = IO(new Bundle {
+    val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value
-    val a = Input(UInt(width.W))
+  }
-    val b = Input(UInt(width.W))
+  object SrcSelect extends ChiselEnum {
-    val op = Input(UInt(4.W))
+    val aSrcRs1, aSrcImm = Value
-    val out = Output(UInt(width.W))
+  }
+  val op = Input(OpSelect())
+  val src = Input(SrcSelect())
+
+  type CtrlTypes = OpSelect.Type :: SrcSelect.Type :: HNil
+  def ctrlBindPorts: CtrlTypes = {
+    op :: src :: HNil
+  }
+}
+
+class ALU[T <: UInt](tpe: T) extends Module {
+  val control = IO(new ALUControlInterface)
+  val in = IO(new Bundle {
+    val a = Input(Vec(control.SrcSelect.all.length, tpe))
+    val b = Input(tpe)
+  })
+  val out = IO(new Bundle {
+    val result = Output(tpe)
   })
 
-  val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0)  // take (-b) if sub
+  val a = in.a(control.src.asUInt)
-  val add = io.a + adder_b
-  val and = io.a & io.b
-  val not = ~io.a
-  val or = io.a | io.b
-  val xor = io.a ^ io.b
-  val slt = io.a < io.b
-  val eq = io.a === io.b
 
-  io.out := MuxLookup(io.op, 0.U)(Seq(
+  // val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0)  // take (-b) if sub
-    0.U -> add,
+  val add = a + in.b 
-    1.U -> add, // add with b reversed
+  val sub = a - in.b
-    2.U -> not,
+  val and = a & in.b
-    3.U -> and,
+  val not = ~a
-    4.U -> or,
+  val or = a | in.b
-    5.U -> xor,
+  val xor = a ^ in.b
-    6.U -> slt,
+  val slt = a < in.b
-    7.U -> eq,
+  val eq = a === in.b
+
+  import control.OpSelect._
+
+  out.result := MuxLookup(control.op, 0.U)(Seq(
+    aOpAdd -> add,
+    aOpSub -> sub,
+    aOpNot -> not,
+    aOpAnd -> and,
+    aOpOr  -> or,
+    aOpXor -> xor,
+    aOpSlt -> slt,
+    aOpEq -> eq
   ))
 }
+
+object ALU {
+  def apply[T <: UInt](tpe: T): ALU[T] = {
+    Module(new ALU(tpe))
+  }
+}

npc/core/src/main/scala/Main.scala

@@ -1,44 +1,129 @@
-package npc
+package flow
 
+import scala.reflect.runtime.universe._
 import chisel3._
 import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
 import chisel3.util.{SRAM}
+import chisel3.util.experimental.decode.{decoder, TruthTable}
 import chisel3.stage.ChiselOption
-import npc.util.{ KeyboardSegController, RegisterFile }
+import chisel3.util.log2Ceil
-import flowpc.components.ProgramCounter
+import chisel3.util.BitPat
+import chisel3.util.Enum
+import chisel3.experimental.prefix
+import shapeless.{HNil, ::}
+import shapeless.HList
+import shapeless.ops.coproduct.Prepend
+import chisel3.util.{ BinaryMemoryFile, HexMemoryFile }
 
-class Switch extends Module {
+object RV32Inst {
-  val io = IO(new Bundle {
+  private val bp = BitPat
-    val sw = Input(Vec(2, Bool()))
+  val addi = this.bp("b???????_?????_?????_000_?????_00100_11")
-    val out = Output(Bool())
+  val inv = this.bp("b???????_?????_?????_???_?????_?????_??")
+}
+
+class PcControl(width: Int) extends Bundle {
+  object SrcSelect extends ChiselEnum {
+    val pPC, pExeResult = Value
+  }
+  val srcSelect = Output(SrcSelect())
+}
+
+import flow.components.{RegControl, PcControlInterface, ALUControlInterface}
+class Control(width: Int) extends Module {
+  val inst = IO(Input(UInt(width.W)))
+
+  val reg = IO(Flipped(new RegControl))
+  val pc = IO(Flipped(new PcControlInterface))
+  val alu = IO(Flipped(new ALUControlInterface))
+
+  // TODO: Add .ctrlTypes together instead of writing them by hand.
+  type T =
+    Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: alu.SrcSelect.Type :: HNil
+  val dst: T = reg.ctrlBindPorts ++ pc.ctrlBindPorts ++ alu.ctrlBindPorts
+
+  val dstList = dst.toList
+  val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
+  val slices = reversePrefixSum.zip(reversePrefixSum.tail)
+
+  import reg.WriteSelect._
+  import pc.SrcSelect._
+  import alu.OpSelect._
+  import alu.SrcSelect._
+  import RV32Inst._
+  val ControlMapping: Array[(BitPat, T)] = Array(
+    //     Regs                       :: PC         :: Exe
+    //     writeEnable :: writeSelect :: srcSelect  ::
+    (addi, true.B      :: rAluOut     :: pStaticNpc :: aOpAdd :: aSrcImm :: HNil),
+  )
+  val default = BitPat.dontCare(dstList.map(_.getWidth).reduce(_ + _))
+
+  def toBits(t: T): BitPat = {
+    val list: List[Data] = t.toList
+    list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _)
+  }
+  val out = decoder(
+    inst,
+    TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default))
+  val srcList = slices.map(s => out(s._1 - 1, s._2))
+
+  srcList
+    .zip(dstList.reverse)
+    .foreach({ case (src, dst) =>
+      dst := src.asTypeOf(dst)
     })
-
-  io.out := io.sw(0) ^ io.sw(1)
 }
 
-import npc.util.{PS2Port, KeyboardController, SegControllerGenerator}
+import flow.components.{RegisterFile, RegFileInterface, ProgramCounter, ALU}
+import chisel3.util.experimental.loadMemoryFromFileInline
+class Flow extends Module {
+  val dataType = UInt(32.W)
 
-class Keyboard extends Module {
+  val ram = SRAM(
-  val io = IO(new Bundle {
+    size = 1024,
-    val ps2 = PS2Port()
+    tpe = dataType,
-    val segs = Output(Vec(8, UInt(8.W)))
+    numReadPorts = 2,
-  })
+    numWritePorts = 1,
+    numReadwritePorts = 0,
+    memoryFile = HexMemoryFile("./resource/addi.txt")
+  )
+  val control = Module(new Control(32))
+  val reg = RegisterFile(32, dataType, 2, 2)
+  val pc = Module(new ProgramCounter(dataType))
+  val alu = Module(new ALU(dataType))
 
-  val seg_handler = Module(new KeyboardSegController)
+  ram.readPorts(0).enable := true.B
-  val keyboard_controller = Module(new KeyboardController)
+  ram.readPorts(0).address := pc.out - 0x80000000L.U
+  val inst = ram.readPorts(0).data
 
-  seg_handler.io.keycode <> keyboard_controller.io.out
+  import control.pc.SrcSelect._
 
-  keyboard_controller.io.ps2 := io.ps2
+  pc.in.pcSrcs(pStaticNpc.litValue.toInt) := pc.out + 4.U
-  io.segs := seg_handler.io.segs
+  pc.in.pcSrcs(pBranchResult.litValue.toInt) := alu.out.result
+
+  control.inst := inst
+  reg.control <> control.reg
+  pc.control <> control.pc
+  alu.control <> control.alu
+
+  import control.reg.WriteSelect._
+  reg.in.writeData(rAluOut.litValue.toInt) := alu.out.result
+  // TODO: Read address in load command goes here
+  ram.readPorts(1).enable := false.B
+  ram.readPorts(1).address := 0.U
+  reg.in.writeData(rMemOut.litValue.toInt) := ram.readPorts(1).data
+  reg.in.writeAddr := inst(11, 7)
+  reg.in.rs(0) := inst(19, 15)
+  reg.in.rs(1) := inst(24, 20)
+
+  // TODO: Memory write goes here
+  ram.writePorts(0).address := 1.U
+  ram.writePorts(0).data := 1.U
+  ram.writePorts(0).enable := false.B
+
+  import control.alu.SrcSelect._
+  alu.in.a(aSrcRs1.litValue.toInt) := reg.out.src(0)
+  alu.in.a(aSrcImm.litValue.toInt) := inst(31, 20)
+  alu.in.b := reg.out.src(1)
+
+  dontTouch(control.out)
 }
-
-<<<<<<< Updated upstream
-=======
-class Flowpc extends Module {
-  val io = IO(new Bundle { })
-  val register_file = new RegisterFile(readPorts = 2);
-  val pc = new ProgramCounter(32);
-  val adder = new SRAM()
-}
->>>>>>> Stashed changes

npc/core/src/main/scala/ProgramCounter.scala

@@ -1,11 +1,39 @@
-package flowpc.components
+package flow.components
 import chisel3._
-import chisel3.util.{Valid}
+import chisel3.util.{Valid, log2Ceil}
+import chisel3.util.MuxLookup
+import shapeless.{HNil, ::}
 
-class ProgramCounter (width: Int) extends Module {
+class PcControlInterface extends Bundle {
-  val io = new Bundle {
+  object SrcSelect extends ChiselEnum {
-    val next_pc = Input(Flipped(Valid(UInt(width.W))))
+    val pStaticNpc, pBranchResult = Value
-    val pc = Output(UInt(width.W))
+  }
+
+  val srcSelect = Input(SrcSelect())
+
+  type CtrlTypes = SrcSelect.Type :: HNil
+  def ctrlBindPorts: CtrlTypes = {
+    srcSelect :: HNil
+  }
+}
+
+class ProgramCounter[T <: Data](tpe: T) extends Module {
+
+  val control = IO(new PcControlInterface)
+  val in = IO(new Bundle {
+    val pcSrcs = Input(Vec(control.SrcSelect.all.length, tpe))
+  })
+  val out = IO(Output(tpe))
+
+  private val pc = RegInit(0x80000000L.U)
+
+  pc := in.pcSrcs(control.srcSelect.asUInt)
+  out := pc
+}
+
+object ProgramCounter {
+  def apply[T <: Data](tpe: T): ProgramCounter[T] = {
+    val pc = Module(new ProgramCounter(tpe))
+    pc
   }
-    io.pc := Mux(io.next_pc.valid, io.next_pc.bits, io.pc)
 }

npc/core/src/main/scala/RegisterFile.scala

@@ -1,17 +1,23 @@
-package flowpc.components
+package flow.components
 
 import chisel3._
 import chisel3.util.log2Ceil
 import chisel3.util.UIntToOH
 import chisel3.util.MuxLookup
+import shapeless.{ HNil, :: }
 
 class RegControl extends Bundle {
-  val writeEnable = Input(Bool()) 
-
   object WriteSelect extends ChiselEnum {
     val rAluOut, rMemOut = Value
   }
+
+  val writeEnable = Input(Bool()) 
   val writeSelect = Input(WriteSelect())
+
+  type CtrlTypes = Bool :: WriteSelect.Type :: HNil
+  def ctrlBindPorts: CtrlTypes = {
+    writeEnable :: writeSelect :: HNil
+  }
 }
 
 class RegFileData[T <: Data](size:Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
@@ -27,7 +33,15 @@ class RegFileData[T <: Data](size:Int, tpe: T, numReadPorts: Int, numWritePorts:
 
 class RegFileInterface[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
   val control = new RegControl
-  val data = new RegFileData(size, tpe, numReadPorts, numWritePorts)
+  // val data = new RegFileData(size, tpe, numReadPorts, numWritePorts)
+  val in = new Bundle {
+    val writeAddr = Input(UInt(size.W))
+    val writeData = Input(Vec(numWritePorts, tpe))
+    val rs = Input(Vec(numReadPorts, UInt(size.W)))
+  }
+  val out = new Bundle {
+    val src = Output(Vec(numReadPorts, tpe))
+  }
 }
 
 class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends Module {
@@ -52,6 +66,7 @@ class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends
   for (readPort <- readPorts) {
     readPort.data := regFile(readPort.addr)
   }
+  dontTouch(regFile)
 }
 
 object RegisterFile {
@@ -60,13 +75,11 @@ object RegisterFile {
     val _out = Wire(new RegFileInterface(size, tpe, numReadPorts, numWritePorts))
     val clock = core.clock
     for (i <- 0 until numReadPorts) {
-      core.readPorts(i).addr := _out.data.read(i).rs
+      core.readPorts(i).addr := _out.in.rs(i)
-      _out.data.read(i).src := core.readPorts(i).data
+      _out.out.src(i) := core.readPorts(i).data
     }
-    core.writePort.addr := _out.data.write.addr
+    core.writePort.addr := _out.in.writeAddr
-    core.writePort.data := MuxLookup(_out.control.writeSelect, 0.U)(
+    core.writePort.data := _out.in.writeData(_out.control.writeSelect.asUInt)
-      _out.control.WriteSelect.all.map(x => (x -> _out.data.write.data(x.asUInt).asUInt))
-    )
     core.writePort.enable := _out.control.writeEnable
     _out
   }

npc/core/src/test/scala/Main.scala

@@ -1,105 +1,47 @@
-package npc
+package flow
 
 import chisel3._
 import chiseltest._
 import org.scalatest.freespec.AnyFreeSpec
 import chiseltest.simulator.WriteVcdAnnotation
 
-import npc.util._
+import flow.Flow
 
-class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
+class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
-  "RegisterFile should work" - {
+  "MemoryFile" - {
-    "with 2 read ports" in {
+    "correctly load" in {
-      test(new RegisterFile(2)) { c =>
+      import chisel3.util.{SRAM, SRAMInterface, HexMemoryFile}
-        def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
+      class UserMem extends Module {
-          c.io.readAddr(port).poke(addr.U)
+        val io = IO(new SRAMInterface(1024, UInt(32.W), 1, 1, 0))
-          c.io.readData(port).expect(value.U)
+        val memoryFile = HexMemoryFile("../resource/addi.txt") 
+        io :<>= SRAM(
+          size = 1024,
+          tpe = UInt(32.W),
+          numReadPorts = 1,
+          numWritePorts = 1,
+          numReadwritePorts = 0,
+          memoryFile = memoryFile
+        )
+        
+        val read = io.readPorts(0).data
+        printf(cf"memoryFile=$memoryFile, readPort=$read%x\n")
       }
-        def write(addr: Int, value: Int): Unit = {
+      test(new UserMem).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
-          c.io.writeEnable.poke(true.B)
+        c.io.readPorts(0).enable.poke(true.B)
-          c.io.writeData.poke(value.U)
+        c.io.writePorts(0).enable.poke(false.B)
-          c.io.writeAddr.poke(addr.U)
+        c.io.writePorts(0).address.poke(0.U)
+        c.io.writePorts(0).data.poke(0.U)
+        for (i <- 0 until 32) {
+          c.io.readPorts(0).address.poke(i.U)
           c.clock.step(1)
-          c.io.writeEnable.poke(false.B)
-        }
-        // everything should be 0 on init
-        for (i <- 0 until 32) {
-          readExpect(i, 0, port = 0)
-          readExpect(i, 0, port = 1)
-        }
-
-        // write 5 * addr + 3
-        for (i <- 0 until 32) {
-          write(i, 5 * i + 3)
-        }
-
-        // check that the writes worked
-        for (i <- 0 until 32) {
-          readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
         }
       }
     }
   }
+  "should compile" in {
+    test(new Flow) { c =>
+      c.clock.step(1)
+    }
   }
 
-class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
-  "With 32 width, " - {
-    val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
-    val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
-    val mask = BigInt("FFFFFFFF", 16)
-    val oprands: List[(BigInt, BigInt)] = List(
-      (5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
-    )
-    val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
-      0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
-      1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
-      2 -> ((a, _) => not(a)),
-      3 -> (_ & _),
-      4 -> (_ | _),
-      5 -> (_ ^ _),
-      6 -> ((a, b) => if (a < b) 1 else 0),
-      7 -> ((a, b) => if (a == b) 1 else 0),
-    )
-    val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
-      c.io.op.poke(op.U)
-      oprands.foreach({ case (a, b) =>
-        c.io.a.poke(a.U)
-        c.io.b.poke(b.U)
-        c.io.out.expect(operations(op)(a, b))
-      })
-    }
-    "add should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
-    }
-    "sub should work" - {
-      "with positive result" in {
-        test(new ALUGenerator(32)) { c =>
-          validate(c, 1, oprands.filter({case (a, b) => a >= b}))
-        }
-      }
-      "with negative result" in {
-        test(new ALUGenerator(32)) { c =>
-          validate(c, 1, oprands.filter({case (a, b) => a < b}))
-        }
-      }
-    }
-    "not should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
-    }
-    "and should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
-    }
-    "or should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
-    }
-    "xor should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
-    }
-    "compare should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
-    }
-    "equal should work" in {
-      test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
-    }
-  }
 }

npc/core/src/test/scala/RegisterFile.scala

@@ -1,11 +1,11 @@
-package flowpc
+package flow
 
 import chisel3._
 import chiseltest._
 import org.scalatest.freespec.AnyFreeSpec
 import chiseltest.simulator.WriteVcdAnnotation
 
-import flowpc.components._
+import flow.components._
 class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
   "RegisterFileCore" - {
     "register 0 is always 0" in {
@@ -41,22 +41,40 @@ class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
     }
   }
   "RegisterInterface" - {
-    "worked" in {
     class Top extends Module {
       val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2))
       val rf = RegisterFile(32, UInt(32.W), 2, 2)
       io :<>= rf
     }
+    "write" in {
       test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
         import c.io.control.WriteSelect._
         val writePort = rAluOut.litValue.toInt
         c.io.control.writeEnable.poke(true)
         c.io.control.writeSelect.poke(rAluOut)
-        c.io.data.write.addr.poke(5)
+        c.io.in.writeAddr.poke(5)
-        c.io.data.write.data(writePort).poke(0xcdef)
+        c.io.in.writeData(writePort).poke(0xcdef)
-        c.io.data.read(0).rs.poke(5)
+        c.io.in.rs(0).poke(5)
         c.clock.step(1)
-        c.io.data.read(0).src.expect(0xcdef)
+        c.io.out.src(0).expect(0xcdef)
+      }
+    }
+    "no data is written when not enabled" in {
+      test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
+        import c.io.control.WriteSelect._
+        val writePort = rAluOut.litValue.toInt
+        c.io.control.writeEnable.poke(true)
+        c.io.control.writeSelect.poke(rAluOut)
+        c.io.in.writeAddr.poke(5)
+        c.io.in.writeData(writePort).poke(0xcdef)
+        c.io.in.rs(0).poke(5)
+        c.clock.step(1)
+
+        c.io.control.writeEnable.poke(false)
+        c.io.in.writeData(writePort).poke(0x1234)
+        c.clock.step(1)
+
+        c.io.out.src(0).expect(0xcdef)
       }
     }
   }

npc/csrc/Flow/main.cpp

@@ -0,0 +1,43 @@
+#include <cstdlib>
+#include <cassert>
+#include <cstdlib>
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+#include <VFlow.h>
+#define MAX_SIM_TIME 100
+#define VERILATOR_TRACE
+
+int main(int argc, char **argv, char **env) {
+    int sim_time = 0;
+    Verilated::commandArgs(argc, argv);
+
+    VFlow *top = new VFlow;
+
+    Verilated::traceEverOn(true);
+    VerilatedVcdC *m_trace = new VerilatedVcdC; 
+#ifdef VERILATOR_TRACE
+    top->trace(m_trace, 5);
+    m_trace->open("waveform.vcd");
+#endif
+    for (sim_time = 0; sim_time < 10; sim_time++) {
+        top->eval();
+        top->clock = !top->clock;
+        top->reset = 1;
+#ifdef VERILATOR_TRACE
+        m_trace->dump(sim_time);
+#endif
+    }
+    top->reset = 0;
+    for (sim_time = 10; sim_time < MAX_SIM_TIME; sim_time++) {
+        top->eval();
+        top->clock = !top->clock;
+#ifdef VERILATOR_TRACE
+        m_trace->dump(sim_time);
+#endif
+    }
+#ifdef VERILATOR_TRACE
+    m_trace->close();
+#endif
+    delete top;
+    exit(EXIT_SUCCESS);
+}

npc/csrc_nvboard/Flow/main.cpp

@@ -0,0 +1,12 @@
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+// #include <nvboard.h>
+#include <VFlow.h>
+
+const int MAX_SIM_TIME=100;
+
+// void nvboard_bind_all_pins(VFLow* top);
+
+int main(int argc, char **argv, char **env) {
+    return 0;
+}

npc/flake.lock

@@ -5,11 +5,11 @@
         "systems": "systems"
       },
       "locked": {
-        "lastModified": 1701680307,
+        "lastModified": 1710146030,
-        "narHash": "sha256-kAuep2h5ajznlPMD9rnQyffWG8EM/C73lejGofXvdM8=",
+        "narHash": "sha256-SZ5L6eA7HJ/nmkzGG7/ISclqe6oZdOZTNoesiInkXPQ=",
         "owner": "numtide",
         "repo": "flake-utils",
-        "rev": "4022d587cbbfd70fe950c1e2083a02621806a725",
+        "rev": "b1d9ab70662946ef0850d488da1c9019f3a9752a",
         "type": "github"
       },
       "original": {
@@ -20,11 +20,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1704194953,
+        "lastModified": 1709961763,
-        "narHash": "sha256-RtDKd8Mynhe5CFnVT8s0/0yqtWFMM9LmCzXv/YKxnq4=",
+        "narHash": "sha256-6H95HGJHhEZtyYA3rIQpvamMKAGoa8Yh2rFV29QnuGw=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "bd645e8668ec6612439a9ee7e71f7eac4099d4f6",
+        "rev": "3030f185ba6a4bf4f18b87f345f104e6a6961f34",
         "type": "github"
       },
       "original": {
@@ -34,6 +34,22 @@
         "type": "github"
       }
     },
+    "nixpkgs-circt162": {
+      "locked": {
+        "lastModified": 1705645507,
+        "narHash": "sha256-tX3vipIAmNDBA8WNWG4oY4KyTfnm2YieTHO2BhG8ISA=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "7995cae3ad60e3d6931283d650d7f43d31aaa5c7",
+        "type": "github"
+      },
+      "original": {
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "7995cae3ad60e3d6931283d650d7f43d31aaa5c7",
+        "type": "github"
+      }
+    },
     "nur-xin": {
       "inputs": {
         "nixpkgs": [
@@ -41,11 +57,11 @@
         ]
       },
       "locked": {
-        "lastModified": 1704450168,
+        "lastModified": 1707020873,
-        "narHash": "sha256-zOLL35LX83Of64quCyxpyP8rTSO/tgrfHNm52tFo6VU=",
+        "narHash": "sha256-+dNltc7tjgTIyle/I/5siQ5IvPwu+R5Uf6e24CmjLNk=",
         "ref": "refs/heads/master",
-        "rev": "beda2a57d946f392d958755c7bb03ac092a20f42",
+        "rev": "8142717e7154dbaadee0679f0224fe75cebb1735",
-        "revCount": 140,
+        "revCount": 147,
         "type": "git",
         "url": "https://git.xinyang.life/xin/nur.git"
       },
@@ -58,6 +74,7 @@
       "inputs": {
         "flake-utils": "flake-utils",
         "nixpkgs": "nixpkgs",
+        "nixpkgs-circt162": "nixpkgs-circt162",
         "nur-xin": "nur-xin"
       }
     },

npc/flake.nix

@@ -1,6 +1,7 @@
 {
   inputs = {
     nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
+    nixpkgs-circt162.url = "github:NixOS/nixpkgs/7995cae3ad60e3d6931283d650d7f43d31aaa5c7";
     flake-utils.url = "github:numtide/flake-utils";
     nur-xin = {
       url = "git+https://git.xinyang.life/xin/nur.git";
@@ -11,14 +12,17 @@
   outputs = { self, ... }@inputs: with inputs;
     flake-utils.lib.eachDefaultSystem (system:
       let
-        pkgs = nixpkgs.legacyPackages.${system} //
+        pkgs = import nixpkgs { inherit system; config.allowUnfree = true; }//
           { nur.xin = nur-xin.legacyPackages.${system}; };
       in
       {
         devShells.default = with pkgs; mkShell {
+          CHISEL_FIRTOOL_PATH = "${nixpkgs-circt162.legacyPackages.${system}.circt}/bin";
           packages = [
             clang-tools
-            rnix-lsp
+            # rnix-lsp
+            coursier
+            espresso
 
             gdb
             jre
@@ -36,7 +40,7 @@
             cmake
             sbt
             nur.xin.nvboard
-            self.packages.${system}.circt
+            nixpkgs-circt162.legacyPackages.${system}.circt
             yosys
           ];
           buildInputs = [

npc/resource/addi.txt

@@ -0,0 +1,10 @@
+00114113
+00114113
+00114113
+00114113
+00114113
+00114113
+00114113
+00114113
+00114113
+00114113