> configure(npc)
ysyx_22040000 李心杨 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar 1 12:35:11 UTC 2024 x86_64 GNU/Linux 11:54:52 up 2 days 2:45, 2 users, load average: 2.66, 1.60, 1.17
This commit is contained in:
tracer-ysyx
parent
705ee17b3c
commit
f7f19ed102
9 changed files with 257 additions and 133 deletions
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@ -6,10 +6,11 @@ val chiselVersion = "5.1.0"
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lazy val root = (project in file("."))
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.settings(
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name := "ChiselLearning",
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name := "flow",
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libraryDependencies ++= Seq(
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"org.chipsalliance" %% "chisel" % chiselVersion,
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"edu.berkeley.cs" %% "chiseltest" % "5.0.2" % "test"
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"edu.berkeley.cs" %% "chiseltest" % "5.0.2" % "test",
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"com.chuusai" %% "shapeless" % "2.3.3"
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),
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scalacOptions ++= Seq(
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"-language:reflectiveCalls",
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@ -3,17 +3,21 @@ package npc.util
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import chisel3._
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import chisel3.util._
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class ALUGenerator(width: Int) extends Module {
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require(width >= 0)
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object ALUSel extends ChiselEnum {
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val add, sub, not, and, or, xor, slt, eq, nop = Value
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}
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class ALUGenerator[T <: ChiselEnum](width: Int, tpe: T = ALUSel) extends Module {
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val io = IO(new Bundle {
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val a = Input(UInt(width.W))
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val b = Input(UInt(width.W))
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val op = Input(UInt(4.W))
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val out = Output(UInt(width.W))
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val a = Input(UInt(tpe.getWidth.W))
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val b = Input(UInt(tpe.getWidth.W))
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val op = Input(ALUSel())
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val out = Output(UInt(tpe.getWidth.W))
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})
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val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
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val add = io.a + adder_b
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// val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
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val add = io.a + io.b
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val sub = io.a - io.b
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val and = io.a & io.b
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val not = ~io.a
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val or = io.a | io.b
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@ -21,14 +25,14 @@ class ALUGenerator(width: Int) extends Module {
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val slt = io.a < io.b
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val eq = io.a === io.b
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io.out := MuxLookup(io.op, 0.U)(Seq(
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0.U -> add,
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1.U -> add, // add with b reversed
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2.U -> not,
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3.U -> and,
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4.U -> or,
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5.U -> xor,
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6.U -> slt,
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7.U -> eq,
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io.out := MuxLookup(io.op, ALUSel.nop.asUInt)(Seq(
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ALUSel.add -> add,
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ALUSel.sub -> sub,
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ALUSel.not -> not,
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ALUSel.and -> and,
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ALUSel.or -> or,
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ALUSel.xor -> xor,
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ALUSel.slt -> slt,
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ALUSel.eq -> eq
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))
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}
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@ -1,9 +1,18 @@
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package npc
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import scala.reflect.runtime.universe._
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import chisel3._
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import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
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import chisel3.util.{SRAM}
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import chisel3.util.experimental.decode.{decoder, TruthTable, QMCMinimizer}
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import chisel3.stage.ChiselOption
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import npc.util.KeyboardSegController
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import npc.util.{ KeyboardSegController }
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import flowpc.components.RegisterFile
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import chisel3.util.log2Ceil
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import chisel3.util.BitPat
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import chisel3.util.Enum
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import chisel3.experimental.prefix
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import shapeless.{ HNil, :: }
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class Switch extends Module {
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val io = IO(new Bundle {
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@ -31,3 +40,58 @@ class Keyboard extends Module {
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io.segs := seg_handler.io.segs
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}
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object RV32Inst {
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private val bp = BitPat
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val addi = this.bp("b??b?????_?????_?????_000_?????_00100_11")
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val inv = this.bp("b???????_?????_?????_???_?????_?????_??")
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}
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class PcControl(width: Int) extends Bundle {
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object SrcSelect extends ChiselEnum {
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val pPC, pExeResult = Value
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}
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val srcSelect = Output(SrcSelect())
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}
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import flowpc.components.{ RegisterFile }
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class Control(width: Int) extends Module {
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val reg = Flipped(RegisterFile(32, UInt(32.W), 2, 2))
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val pc = new PcControl(width)
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val inst = IO(Input(UInt(width.W)))
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type T = Bool :: reg.control.WriteSelect.Type :: HNil
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val dst: T = reg.control.writeEnable :: reg.control.writeSelect :: HNil
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val dstList: List[Data] = dst.toList
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val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
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val slices = reversePrefixSum.zip(reversePrefixSum.tail)
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import reg.control.WriteSelect._
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import pc.SrcSelect._
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import RV32Inst._
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val ControlMapping: Array[(BitPat, T)] = Array(
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// Regs :: PC :: Exe
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// writeEnable :: writeSelect :: srcSelect ::
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(addi, false.B :: rAluOut :: HNil)
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)
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def toBits(t: T): BitPat = {
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val list: List[Data] = t.toList
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list.map(x => x.asUInt).map(x => BitPat(x)).reduce(_ ## _)
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}
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val out = decoder(QMCMinimizer, inst, TruthTable(
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ControlMapping.map(it => (it._1, toBits(it._2))), inv))
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val srcList = slices.map(s => out(s._1 - 1, s._2))
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srcList.zip(dstList).foreach({ case (src, dst) => dst := src })
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}
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class Flowpc extends Module {
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val io = IO(new Bundle { })
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val ram = SRAM(size=128*1024*1024, tpe=UInt(32.W), numReadPorts=2, numWritePorts=1,numReadwritePorts=0)
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// Instruction Fetch
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ram.readPorts(0).enable := true.B
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val instruction = ram.readPorts(0).address
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}
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13
npc/core/src/main/scala/ProgramCounter.scala
Normal file
13
npc/core/src/main/scala/ProgramCounter.scala
Normal file
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@ -0,0 +1,13 @@
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package flowpc.components
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import chisel3._
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import chisel3.util.{Valid, log2Ceil}
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import chisel3.util.MuxLookup
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class ProgramCounter[T <: Data](tpe: T, numPcSrc: Int) extends Module {
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val io = new Bundle {
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val pc_srcs = Input(Vec(numPcSrc, tpe))
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val select = Input(UInt(log2Ceil(numPcSrc).W))
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val pc = Output(tpe)
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}
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io.pc := io.pc_srcs(io.select)
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}
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@ -1,25 +1,72 @@
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package npc.util
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package flowpc.components
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import chisel3._
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import chisel3.util.log2Ceil
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import chisel3.util.UIntToOH
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import chisel3.util.MuxLookup
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class RegisterFile(readPorts: Int) extends Module {
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require(readPorts >= 0)
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val io = IO(new Bundle {
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val writeEnable = Input(Bool())
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val writeAddr = Input(UInt(5.W))
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val writeData = Input(UInt(32.W))
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val readAddr = Input(Vec(readPorts, UInt(5.W)))
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val readData = Output(Vec(readPorts, UInt(32.W)))
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})
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class RegControl extends Bundle {
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val writeEnable = Input(Bool())
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val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
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for (i <- 1 until 32) {
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regFile(i) := regFile(i)
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object WriteSelect extends ChiselEnum {
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val rAluOut, rMemOut = Value
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}
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regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
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regFile(0) := 0.U
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val writeSelect = Input(WriteSelect())
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}
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for (i <- 0 until readPorts) {
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io.readData(i) := regFile(io.readAddr(i))
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class RegFileData[T <: Data](size:Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
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val write = new Bundle {
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val addr = Input(UInt(size.W))
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val data = Vec(numWritePorts, Input(tpe))
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}
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val read = Vec(numReadPorts, new Bundle {
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val rs = Input(UInt(size.W))
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val src = Output(tpe)
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})
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}
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class RegFileInterface[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
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val control = new RegControl
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val data = new RegFileData(size, tpe, numReadPorts, numWritePorts)
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}
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class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends Module {
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printf("$numReadPorts\n")
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require(numReadPorts >= 0)
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val writePort = IO(new Bundle {
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val enable = Input(Bool())
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val addr = Input(UInt(size.W))
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val data = Input(tpe)
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})
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val readPorts = IO(Vec(numReadPorts, new Bundle {
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val addr = Input(UInt(size.W))
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val data = Output(tpe)
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}))
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// val regFile = RegInit(VecInit(Seq.fill(size)(0.U)))
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// val writeAddrOH = UIntToOH(writePort.addr)
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// for ((reg, i) <- regFile.zipWithIndex) {
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// reg := Mux(writeAddrOH(i) && writePort.enable, writePort.data, reg)
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// }
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// for (readPort <- readPorts) {
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// readPort.data := regFile(readPort.addr)
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// }
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}
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object RegisterFile {
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def apply[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int): RegFileInterface[T] = {
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val core = new RegisterFileCore(size, tpe, numReadPorts)
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val _out = Wire(new RegFileInterface(size, tpe, numReadPorts, numWritePorts))
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val clock = core.clock
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for (i <- 0 to numReadPorts) {
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core.readPorts(i).addr := _out.data.read(i).rs
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core.readPorts(i).data := _out.data.read(i).src
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}
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core.writePort.addr := _out.data.write.addr
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core.writePort.data := MuxLookup(_out.control.writeSelect, 0.U)(
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_out.control.WriteSelect.all.map(x => (x -> _out.data.write.data(x.asUInt).asUInt))
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)
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_out
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}
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}
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@ -7,99 +7,64 @@ import chiseltest.simulator.WriteVcdAnnotation
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import npc.util._
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFile should work" - {
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"with 2 read ports" in {
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test(new RegisterFile(2)) { c =>
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def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
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c.io.readAddr(port).poke(addr.U)
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c.io.readData(port).expect(value.U)
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}
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def write(addr: Int, value: Int): Unit = {
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c.io.writeEnable.poke(true.B)
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c.io.writeData.poke(value.U)
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c.io.writeAddr.poke(addr.U)
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c.clock.step(1)
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c.io.writeEnable.poke(false.B)
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}
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// everything should be 0 on init
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for (i <- 0 until 32) {
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readExpect(i, 0, port = 0)
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readExpect(i, 0, port = 1)
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}
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// write 5 * addr + 3
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for (i <- 0 until 32) {
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write(i, 5 * i + 3)
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}
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// check that the writes worked
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for (i <- 0 until 32) {
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readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
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}
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}
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}
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}
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}
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class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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"With 32 width, " - {
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val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
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val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
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val mask = BigInt("FFFFFFFF", 16)
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val oprands: List[(BigInt, BigInt)] = List(
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(5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
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)
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val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
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0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
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1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
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2 -> ((a, _) => not(a)),
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3 -> (_ & _),
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4 -> (_ | _),
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5 -> (_ ^ _),
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6 -> ((a, b) => if (a < b) 1 else 0),
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7 -> ((a, b) => if (a == b) 1 else 0),
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)
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val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
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c.io.op.poke(op.U)
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oprands.foreach({ case (a, b) =>
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c.io.a.poke(a.U)
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c.io.b.poke(b.U)
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c.io.out.expect(operations(op)(a, b))
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})
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}
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"add should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
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}
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"sub should work" - {
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"with positive result" in {
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test(new ALUGenerator(32)) { c =>
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validate(c, 1, oprands.filter({case (a, b) => a >= b}))
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}
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}
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"with negative result" in {
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test(new ALUGenerator(32)) { c =>
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validate(c, 1, oprands.filter({case (a, b) => a < b}))
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}
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}
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}
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"not should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
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}
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"and should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
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}
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"or should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
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}
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"xor should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
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}
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"compare should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
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}
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"equal should work" in {
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test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
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}
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}
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}
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// class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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// "With 32 width, " - {
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// val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
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// val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
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// val mask = BigInt("FFFFFFFF", 16)
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// val oprands: List[(BigInt, BigInt)] = List(
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// (5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
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// )
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// val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
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// 0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
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// 1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
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// 2 -> ((a, _) => not(a)),
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// 3 -> (_ & _),
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// 4 -> (_ | _),
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// 5 -> (_ ^ _),
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// 6 -> ((a, b) => if (a < b) 1 else 0),
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// 7 -> ((a, b) => if (a == b) 1 else 0),
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// )
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// val validate = (c: ALUGenerator[32], op: Int, oprands: List[(BigInt, BigInt)]) => {
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// c.io.op.poke(op.U)
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// oprands.foreach({ case (a, b) =>
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// c.io.a.poke(a.U)
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// c.io.b.poke(b.U)
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// c.io.out.expect(operations(op)(a, b))
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// })
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// }
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// "add should work" in {
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// test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
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// }
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// "sub should work" - {
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// "with positive result" in {
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// test(new ALUGenerator(32)) { c =>
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// validate(c, 1, oprands.filter({case (a, b) => a >= b}))
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// }
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// }
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// "with negative result" in {
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// test(new ALUGenerator(32)) { c =>
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// validate(c, 1, oprands.filter({case (a, b) => a < b}))
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// }
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// }
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// }
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// "not should work" in {
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// test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
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// }
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// "and should work" in {
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// test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
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// }
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// "or should work" in {
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// test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
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// }
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// "xor should work" in {
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// test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
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// }
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// "compare should work" in {
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// test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
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// }
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// "equal should work" in {
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// test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
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// }
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// }
|
||||
// }
|
||||
|
|
|
|||
29
npc/core/src/test/scala/RegisterFile.scala
Normal file
29
npc/core/src/test/scala/RegisterFile.scala
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
package flowpc
|
||||
|
||||
import chisel3._
|
||||
import chiseltest._
|
||||
import org.scalatest.freespec.AnyFreeSpec
|
||||
import chiseltest.simulator.WriteVcdAnnotation
|
||||
|
||||
import flowpc.components._
|
||||
|
||||
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
|
||||
"RegisterFileCore" - {
|
||||
"(0) is always 0" - {
|
||||
// val reg = new RegisterFileCore(32, UInt(32.W), 2)
|
||||
test(new RegisterFileCore(32, UInt(32.W), 2)).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
|
||||
c.readPorts(0).addr.poke(0)
|
||||
c.readPorts(1).addr.poke(0)
|
||||
c.writePort.enable.poke(true)
|
||||
c.writePort.addr.poke(0)
|
||||
c.writePort.data.poke(0xdeadbeef)
|
||||
|
||||
c.readPorts(0).data.expect(0)
|
||||
c.readPorts(1).data.expect(0)
|
||||
c.clock.step(1)
|
||||
c.readPorts(0).data.expect(0)
|
||||
c.readPorts(1).data.expect(0)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -19,6 +19,7 @@
|
|||
packages = [
|
||||
clang-tools
|
||||
rnix-lsp
|
||||
coursier
|
||||
|
||||
gdb
|
||||
jre
|
||||
|
|
|
|||
Loading…
Reference in a new issue