> configure
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 00:40:41 up 1 day 9:27, 2 users, load average: 0.35, 0.36, 0.37
This commit is contained in:
tracer-ysyx
parent
0e11c2e0fb
commit
f0ce5198cf
13 changed files with 271 additions and 137 deletions
2
.gitignore
vendored
2
.gitignore
vendored
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@ -1,5 +1,3 @@
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*.*
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*
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!*/
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!/nemu/*
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!/nexus-am/*
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@ -1,55 +0,0 @@
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#/usr/bin/env bash
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#
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# Environment Variables:
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# NEMU_HOME
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set -x
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STUID=ysyx_22040000
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STUNAME=李心杨
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TRACER=tracer-ysyx
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GITFLAGS="-q --author=$TRACER<tracer@ysyx.org> --no-verify --allow-empty"
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YSYX_HOME=$NEMU_HOME/..
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WORK_BRANCH=$(git rev-parse --abbrev-ref HEAD)
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WORK_INDEX=$YSYX_HOME/.git/index.${WORK_BRANCH}
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TRACER_BRANCH=$TRACER
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LOCK_DIR=$YSYX_HOME/.git/
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git_soft_checkout () {
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git checkout --detach -q && git reset --soft $1 -q -- && git checkout $1 -q -- ;
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}
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git_commit () {
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# create tracer branch if not existent
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git branch $TRACER_BRANCH -q 2>/dev/null || true
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# backup git index
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cp -a .git/index $WORK_INDEX
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# switch to tracer branch
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git_soft_checkout "$TRACER_BRANCH"
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# add files to commit
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git add . -A --ignore-errors
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# generate commit msg, commit changes in tracer branch
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printf "> $1 \n $STUID $STUNAME \n $(uname -a) \n $(uptime)\n" | git commit -F - $GITFLAGS
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git_soft_checkout "$WORK_BRANCH"
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mv $WORK_INDEX .git/index
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}
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git_commit $1
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# TIMEOUT=2
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# LOCKFILE=$YSYX_HOME/.git/index.lock
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# exec {FD}<>$LOCKFILE
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# if ! flock -x -w $TIMEOUT $FD; then
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# echo "Failed to obtain a lock within $TIMEOUT seconds"
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# echo "Another instance of `basename $0` is probably running."
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# exit 1
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# else
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# echo "Lock acquired"
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# git_commit $1
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# rm -f $WORK_INDEX
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# exit 0
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# fi
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12
npc/.gitignore
vendored
12
npc/.gitignore
vendored
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@ -1,17 +1,11 @@
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!Makefile
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!*.mk
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!*.[cSh]
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!*.v
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!*.cc
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!*.cpp
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!.gitignore
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!README.md
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build/
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**/project/
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**/target/
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*.class
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*.log
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.cache/
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.bsp/
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**/.bsp/
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.bloop/
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.metals/
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@ -1,29 +1,90 @@
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cmake_minimum_required(VERSION 3.10)
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cmake_minimum_required(VERSION 3.20)
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project(NPC_xin)
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project(npc)
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set (CMAKE_CXX_STANDARD 11)
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cmake_policy(SET CMP0144 NEW)
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find_package(verilator)
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if (NOT verilator_FOUND)
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message(FATAL_ERROR "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable")
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endif()
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if(NOT DEFINED NVBOARD_HOME)
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set(NVBOARD_HOME get_filename_component(real_path "../nvboard" REALPATH))
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endif()
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add_library(nvboard STATIC IMPORTED)
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set_target_properties(bar PROPERTIES
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IMPORTED_LOCATION "${NVBOARD_HOME}/build/nvboard.a"
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INTERFACE_INCLUDE_DIRECTORIES "${CMAKE_SOURCE_DIR}/include/libbar"
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execute_process(
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COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "configure npc"
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WORKING_DIRECTORY ../
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)
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add_executable(Main csrc/main.cpp)
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add_executable(Main_nvboard csrc_nvboard/main.cpp)
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find_package(SDL2 REQUIRED)
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find_package(SDL2_image REQUIRED)
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verilate(Main
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COVERAGE TRACE
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SOURCES build/chisel/Main.sv build/chisel/RegisterFile.sv)
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find_package(verilator REQUIRED)
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verilate(Main_nvboard
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COVERAGE TRACE
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SOURCES build/chisel/Main.sv build/chisel/RegisterFile.sv)
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find_library(NVBOARD_LIBRARY NAMES nvboard)
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find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h)
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set(TOPMODULE "Switch")
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set(SCALA_CORE "${CMAKE_CURRENT_SOURCE_DIR}/core")
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set(CHISEL_MODULE_CLASS "${CMAKE_PROJECT_NAME}.${TOPMODULE}")
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file(GLOB_RECURSE SCALA_CORE_SOURCES "${SCALA_CORE}/src/main/scala/*.scala")
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file(GLOB_RECURSE SCALA_CORE_TEST_SOURCES "${SCALA_CORE}/src/test/scala/*.scala")
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# Configure time verilog source generation for verilator
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execute_process(
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COMMAND sbt "runMain circt.stage.ChiselMain --target-dir ${CMAKE_CURRENT_BINARY_DIR}/vsrc --module ${CHISEL_MODULE_CLASS} --target verilog"
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WORKING_DIRECTORY ${SCALA_CORE}
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)
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add_custom_command(
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OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/vsrc/${TOPMODULE}.v
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COMMAND sbt "runMain circt.stage.ChiselMain --target-dir ${CMAKE_CURRENT_BINARY_DIR}/vsrc --module ${CHISEL_MODULE_CLASS} --target verilog"
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WORKING_DIRECTORY ${SCALA_CORE}
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DEPENDS ${SCALA_CORE_SOURCES}
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)
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add_custom_target(
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ChiselBuild
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DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/vsrc/${TOPMODULE}.v
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)
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# -- Build NVBoard executable
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add_custom_command(
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OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/auto_bind.cpp
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COMMAND auto_pin_bind ${CMAKE_SOURCE_DIR}/constr/${TOPMODULE}.nxdc ${CMAKE_CURRENT_BINARY_DIR}/auto_bind.cpp
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DEPENDS ${CMAKE_SOURCE_DIR}/constr/${TOPMODULE}.nxdc
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)
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add_executable(V${TOPMODULE}_nvboard csrc_nvboard/main.cpp auto_bind.cpp)
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verilate(V${TOPMODULE}_nvboard TRACE COVERAGE THREADS
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TOP_MODULE ${TOPMODULE}
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PREFIX V${TOPMODULE}
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SOURCES ${CMAKE_CURRENT_BINARY_DIR}/vsrc/${TOPMODULE}.v)
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add_dependencies(V${TOPMODULE}_nvboard ChiselBuild)
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target_include_directories(V${TOPMODULE}_nvboard PRIVATE ${NVBOARD_INCLUDE_DIR} ${SDL2_INCLUDE_DIRS})
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target_link_libraries(V${TOPMODULE}_nvboard PRIVATE ${NVBOARD_LIBRARY} SDL2::SDL2 SDL2_image::SDL2_image)
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install(TARGETS V${TOPMODULE}_nvboard)
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# -- Build Verilator executable and add to test
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add_executable(V${TOPMODULE} csrc/main.cpp)
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verilate(V${TOPMODULE} TRACE COVERAGE THREADS
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TOP_MODULE ${TOPMODULE}
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PREFIX V${TOPMODULE}
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SOURCES ${CMAKE_CURRENT_BINARY_DIR}/vsrc/${TOPMODULE}.v)
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add_dependencies(V${TOPMODULE} ChiselBuild)
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enable_testing()
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add_test(NAME V${TOPMODULE} COMMAND V${TOPMODULE})
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# -- Add build tracking
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add_custom_command(
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TARGET V${TOPMODULE}_nvboard
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COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "Build V${TOPMODULE}_nvboard"
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WORKING_DIRECTORY ../
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)
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add_custom_command(
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TARGET V${TOPMODULE}
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COMMAND ${CMAKE_SOURCE_DIR}/../git_commit.sh "Build V${TOPMODULE}"
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WORKING_DIRECTORY ../
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)
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5
npc/constr/Switch.nxdc
Normal file
5
npc/constr/Switch.nxdc
Normal file
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@ -0,0 +1,5 @@
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top=Switch
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io_sw_0 (SW0)
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io_sw_1 (SW1)
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io_out (LD0)
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64
npc/core/src/main/scala/Reg.scala
Normal file
64
npc/core/src/main/scala/Reg.scala
Normal file
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@ -0,0 +1,64 @@
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package npc
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import chisel3._
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import chisel3.stage.ChiselOption
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class RegisterFile(readPorts: Int) extends Module {
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require(readPorts >= 0)
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val io = IO(new Bundle {
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val writeEnable = Input(Bool())
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val writeAddr = Input(UInt(5.W))
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val writeData = Input(UInt(32.W))
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val readAddr = Input(Vec(readPorts, UInt(5.W)))
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val readData = Output(Vec(readPorts, UInt(32.W)))
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})
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val regFile = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
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for (i <- 1 until 32) {
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regFile(i) := regFile(i)
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}
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regFile(io.writeAddr) := Mux(io.writeEnable, io.writeData, regFile(io.writeAddr))
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regFile(0) := 0.U
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for (i <- 0 until readPorts) {
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io.readData(i) := regFile(io.readAddr(i))
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}
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}
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class MuxGenerator(width: Int, nInput: Int) extends Module {
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require(width >= 0)
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require(nInput >= 1)
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require(nInput.toBinaryString.map(_ - '0').sum == 1)
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val io = IO(new Bundle {
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val in = Input(Vec(nInput, UInt(width.W)))
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val sel = Input(UInt(nInput.toBinaryString.reverse.indexOf('1').W))
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val out = Output(UInt(width.W))
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})
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io.out := io.in(io.sel)
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}
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class Test extends Module {
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val io = IO(new Bundle {
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val in = Input(UInt(32.W))
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val out = Output(UInt(32.W))
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})
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val regFile = Module(new RegisterFile(2))
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regFile.io.writeEnable := true.B
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regFile.io.writeAddr := 1.U
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regFile.io.writeData := io.in
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regFile.io.readAddr(0) := 0.U
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regFile.io.readAddr(1) := 1.U
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io.out := regFile.io.readData(1)
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}
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class Switch extends Module {
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val io = IO(new Bundle {
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val sw = Input(Vec(2, Bool()))
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val out = Output(Bool())
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})
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io.out := io.sw(0) ^ io.sw(1)
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}
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71
npc/core/src/test/scala/Reg.scala
Normal file
71
npc/core/src/test/scala/Reg.scala
Normal file
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@ -0,0 +1,71 @@
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFile should work" - {
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"with 2 read ports" in {
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test(new RegisterFile(2)) { c =>
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def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
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c.io.readAddr(port).poke(addr.U)
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c.io.readData(port).expect(value.U)
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}
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def write(addr: Int, value: Int): Unit = {
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c.io.writeEnable.poke(true.B)
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c.io.writeData.poke(value.U)
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c.io.writeAddr.poke(addr.U)
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c.clock.step(1)
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c.io.writeEnable.poke(false.B)
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}
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// everything should be 0 on init
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for (i <- 0 until 32) {
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readExpect(i, 0, port = 0)
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readExpect(i, 0, port = 1)
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}
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// write 5 * addr + 3
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for (i <- 0 until 32) {
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write(i, 5 * i + 3)
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}
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// check that the writes worked
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for (i <- 0 until 32) {
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readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
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}
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}
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}
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}
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}
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class MuxGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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"MuxGenerator should work" - {
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"when there are 2 inputs" in {
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test(new MuxGenerator(8, 2)) { c =>
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c.io.in(0).poke(0.U)
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c.io.in(1).poke(1.U)
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c.io.sel.poke(0.U)
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c.io.out.expect(0.U)
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c.io.sel.poke(1.U)
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c.io.out.expect(1.U)
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}
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}
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"when there are 1024 inputs" in {
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test(new MuxGenerator(32, 1024)) { c =>
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for (i <- 0 until 1024) {
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c.io.in(i).poke(i.U)
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}
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for (i <- 0 until 1024) {
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c.io.sel.poke(i.U)
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c.io.out.expect(i.U)
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}
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}
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}
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}
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"MuxGenerator should raise exception" - {
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"when nInput is not 2^n" in {
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assertThrows[IllegalArgumentException] {
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test(new MuxGenerator(8, 3)) { c => }
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}
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}
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}
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}
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@ -3,14 +3,14 @@
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#include <cstdlib>
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include <VMain.h>
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#include <VSwitch.h>
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const int MAX_SIM_TIME=100;
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int main(int argc, char **argv, char **env) {
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int sim_time = 0;
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Verilated::commandArgs(argc, argv);
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VMain *top = new VMain;
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VSwitch *top = new VSwitch;
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Verilated::traceEverOn(true);
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VerilatedVcdC *m_trace = new VerilatedVcdC;
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@ -18,16 +18,16 @@ int main(int argc, char **argv, char **env) {
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top->trace(m_trace, 5);
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m_trace->open("waveform.vcd");
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#endif
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// for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
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// CData sw = rand() & 0b11;
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// top->sw = sw;
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// top->eval();
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// printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr);
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// assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) );
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// #ifdef VERILATOR_TRACE
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// m_trace->dump(sim_time);
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||||
// #endif
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||||
// }
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||||
for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
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top->io_sw_0 = rand() % 2;
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||||
top->io_sw_1 = rand() % 2;
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||||
top->eval();
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printf("sw0 = %d, sw1 = %d, ledr = %d\n", top->io_sw_0, top->io_sw_1, top->io_out);
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assert(top->io_out == (top->io_sw_0 ^ top->io_sw_1));
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||||
#ifdef VERILATOR_TRACE
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||||
m_trace->dump(sim_time);
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||||
#endif
|
||||
}
|
||||
#ifdef VERILATOR_TRACE
|
||||
m_trace->close();
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,15 +2,16 @@
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|||
#include <cassert>
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||||
#include <cstdlib>
|
||||
#include <verilated.h>
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||||
#include <VMain.h>
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||||
#include <verilated_vcd_c.h>
|
||||
#include <nvboard.h>
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||||
#include <VSwitch.h>
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||||
|
||||
const int MAX_SIM_TIME=100;
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||||
|
||||
void nvboard_bind_all_pins(VMain* top);
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void nvboard_bind_all_pins(VSwitch* top);
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||||
|
||||
int main(int argc, char **argv, char **env) {
|
||||
VMain* top = new VMain;
|
||||
VSwitch *top = new VSwitch;
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||||
|
||||
nvboard_bind_all_pins(top);
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nvboard_init();
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||||
|
|
|
|||
|
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@ -20,11 +20,11 @@
|
|||
},
|
||||
"nixpkgs": {
|
||||
"locked": {
|
||||
"lastModified": 1703013332,
|
||||
"narHash": "sha256-+tFNwMvlXLbJZXiMHqYq77z/RfmpfpiI3yjL6o/Zo9M=",
|
||||
"lastModified": 1704194953,
|
||||
"narHash": "sha256-RtDKd8Mynhe5CFnVT8s0/0yqtWFMM9LmCzXv/YKxnq4=",
|
||||
"owner": "NixOS",
|
||||
"repo": "nixpkgs",
|
||||
"rev": "54aac082a4d9bb5bbc5c4e899603abfb76a3f6d6",
|
||||
"rev": "bd645e8668ec6612439a9ee7e71f7eac4099d4f6",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
|
|
@ -41,11 +41,11 @@
|
|||
]
|
||||
},
|
||||
"locked": {
|
||||
"lastModified": 1704380403,
|
||||
"narHash": "sha256-eElBXx8ocUCVg6LuHBUXSfCRKYRZfbwURIXcgL/ciJY=",
|
||||
"lastModified": 1704450168,
|
||||
"narHash": "sha256-zOLL35LX83Of64quCyxpyP8rTSO/tgrfHNm52tFo6VU=",
|
||||
"ref": "refs/heads/master",
|
||||
"rev": "2e7a57373f52999d579dcebb1202dc731d71ef35",
|
||||
"revCount": 139,
|
||||
"rev": "beda2a57d946f392d958755c7bb03ac092a20f42",
|
||||
"revCount": 140,
|
||||
"type": "git",
|
||||
"url": "https://git.xinyang.life/xin/nur.git"
|
||||
},
|
||||
|
|
|
|||
|
|
@ -15,31 +15,32 @@
|
|||
{ nur.xin = nur-xin.legacyPackages.${system}; };
|
||||
in
|
||||
{
|
||||
devShells.default = pkgs.mkShell {
|
||||
packages = with pkgs; [
|
||||
gtkwave
|
||||
gdb
|
||||
bear
|
||||
devShells.default = with pkgs; mkShell {
|
||||
packages = [
|
||||
clang-tools
|
||||
rnix-lsp
|
||||
sbt
|
||||
];
|
||||
|
||||
nativeBuildInputs = with pkgs; [
|
||||
cmake
|
||||
verilator
|
||||
scala
|
||||
nur.xin.nvboard
|
||||
self.packages.${system}.circt
|
||||
];
|
||||
|
||||
buildInputs = with pkgs; [
|
||||
gdb
|
||||
jre
|
||||
];
|
||||
|
||||
shellHook = ''
|
||||
export NEMU_HOME=/home/xin/repo/ysyx-workbench/nemu
|
||||
'';
|
||||
inputsFrom = [ self.packages.${system}.default ];
|
||||
};
|
||||
packages.default = with pkgs; clangStdenv.mkDerivation {
|
||||
name = "npc";
|
||||
version = "0.0.1";
|
||||
src = ./.;
|
||||
nativeBuildInputs = [
|
||||
cmake
|
||||
sbt
|
||||
nur.xin.nvboard
|
||||
self.packages.${system}.circt
|
||||
];
|
||||
buildInputs = [
|
||||
verilator
|
||||
nur.xin.nvboard
|
||||
];
|
||||
|
||||
NEMU_HOME="/home/xin/repo/ysyx-workbench/nemu";
|
||||
};
|
||||
|
||||
# This version (1.43.0) of circt does not exist in nixpkgs
|
||||
|
|
|
|||
|
|
@ -1,6 +0,0 @@
|
|||
module top(
|
||||
input [1:0] sw,
|
||||
output ledr
|
||||
);
|
||||
assign ledr = sw[1] ^ sw[0];
|
||||
endmodule
|
||||
Loading…
Reference in a new issue