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> configure(npc)

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ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  11:46:30  up   1:22,  2 users,  load average: 1.63, 1.23, 0.98
This commit is contained in:
tracer-ysyx 2024-03-13 11:46:30 +08:00 committed by xinyangli
parent b0793d3253
commit efcfef915a
2 changed files with 5 additions and 5 deletions
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4
npc/core/src/main/scala/ALU.scala
View file

@ -9,7 +9,7 @@ class ALUControlInterface extends Bundle {
val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value
}
object SrcSelect extends ChiselEnum {
val aSrcRs2, aSrcImm = Value
val aSrcRs1, aSrcImm = Value
}
val op = Input(OpSelect())
val src = Input(SrcSelect())
@ -23,7 +23,7 @@ class ALUControlInterface extends Bundle {
class ALU[T <: UInt](tpe: T) extends Module {
val control = IO(new ALUControlInterface)
val in = IO(new Bundle {
val a = Input(Vec(control.SrcSelect.getWidth, tpe))
val a = Input(Vec(control.SrcSelect.all.length, tpe))
val b = Input(tpe)
})
val out = IO(new Bundle {

6
npc/core/src/main/scala/Main.scala
View file

@ -71,8 +71,6 @@ class Control(width: Int) extends Module {
val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
val slices = reversePrefixSum.zip(reversePrefixSum.tail)
val srcList = slices.map(s => out(s._1 - 1, s._2))
// println(dstList)
// println(srcList)
srcList
.zip(dstList.reverse)
@ -128,7 +126,9 @@ class Flow extends Module {
ram.writePorts(0).data := 1.U
ram.writePorts(0).enable := false.B
alu.in.a := reg.out.src(0)
import control.alu.SrcSelect._
alu.in.a(aSrcRs1.litValue.toInt) := reg.out.src(0)
alu.in.a(aSrcImm.litValue.toInt) := inst(31, 20)
alu.in.b := reg.out.src(1)
dontTouch(control.out)
}