> configure(npc)
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 13:54:52 up 1 day 22:41, 2 users, load average: 2.48, 1.99, 1.57
This commit is contained in:
tracer-ysyx
parent
b4bef0fb64
commit
dd03e43fbd
2 changed files with 282 additions and 6 deletions
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@ -68,12 +68,12 @@ class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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}
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}
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"not should work" in {
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// test(new ALUGenerator(32)) { c =>
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// c.io.op.poke(2.U)
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// c.io.a.poke(5.U)
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// c.io.b.poke(3.U)
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// c.io.out.expect(((1 << 32) - 1 - 5).U)
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// }
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(2.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(BigInt("FFFFFFFA", 16))
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}
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}
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"and should work" in {
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test(new ALUGenerator(32)) { c =>
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@ -0,0 +1,276 @@
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FIRRTL version 1.2.0
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circuit RegisterFile :
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module RegisterFile :
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input clock : Clock
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input reset : UInt<1>
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input io_writeEnable : UInt<1> @[core/src/main/scala/Main.scala 9:14]
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input io_writeAddr : UInt<5> @[core/src/main/scala/Main.scala 9:14]
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input io_writeData : UInt<32> @[core/src/main/scala/Main.scala 9:14]
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input io_readAddr_0 : UInt<5> @[core/src/main/scala/Main.scala 9:14]
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input io_readAddr_1 : UInt<5> @[core/src/main/scala/Main.scala 9:14]
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output io_readData_0 : UInt<32> @[core/src/main/scala/Main.scala 9:14]
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output io_readData_1 : UInt<32> @[core/src/main/scala/Main.scala 9:14]
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reg regFile_0 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_0) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_1 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_1) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_2 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_2) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_3 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_3) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_4 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_4) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_5 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_5) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_6 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_6) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_7 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_7) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_8 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_8) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_9 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_9) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_10 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_10) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_11 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_11) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_12 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_12) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_13 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_13) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_14 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_14) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_15 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_15) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_16 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_16) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_17 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_17) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_18 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_18) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_19 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_19) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_20 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_20) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_21 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_21) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_22 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_22) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_23 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_23) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_24 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_24) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_25 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_25) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_26 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_26) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_27 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_27) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_28 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_28) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_29 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_29) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_30 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_30) @[core/src/main/scala/Main.scala 17:24]
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reg regFile_31 : UInt<32>, clock with :
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reset => (UInt<1>("h0"), regFile_31) @[core/src/main/scala/Main.scala 17:24]
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node _GEN_0 = validif(eq(UInt<1>("h0"), io_writeAddr), regFile_0) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_1 = mux(eq(UInt<1>("h1"), io_writeAddr), regFile_1, _GEN_0) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_2 = mux(eq(UInt<2>("h2"), io_writeAddr), regFile_2, _GEN_1) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_3 = mux(eq(UInt<2>("h3"), io_writeAddr), regFile_3, _GEN_2) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_4 = mux(eq(UInt<3>("h4"), io_writeAddr), regFile_4, _GEN_3) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_5 = mux(eq(UInt<3>("h5"), io_writeAddr), regFile_5, _GEN_4) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_6 = mux(eq(UInt<3>("h6"), io_writeAddr), regFile_6, _GEN_5) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_7 = mux(eq(UInt<3>("h7"), io_writeAddr), regFile_7, _GEN_6) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_8 = mux(eq(UInt<4>("h8"), io_writeAddr), regFile_8, _GEN_7) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_9 = mux(eq(UInt<4>("h9"), io_writeAddr), regFile_9, _GEN_8) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_10 = mux(eq(UInt<4>("ha"), io_writeAddr), regFile_10, _GEN_9) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_11 = mux(eq(UInt<4>("hb"), io_writeAddr), regFile_11, _GEN_10) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_12 = mux(eq(UInt<4>("hc"), io_writeAddr), regFile_12, _GEN_11) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_13 = mux(eq(UInt<4>("hd"), io_writeAddr), regFile_13, _GEN_12) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_14 = mux(eq(UInt<4>("he"), io_writeAddr), regFile_14, _GEN_13) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_15 = mux(eq(UInt<4>("hf"), io_writeAddr), regFile_15, _GEN_14) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_16 = mux(eq(UInt<5>("h10"), io_writeAddr), regFile_16, _GEN_15) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_17 = mux(eq(UInt<5>("h11"), io_writeAddr), regFile_17, _GEN_16) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_18 = mux(eq(UInt<5>("h12"), io_writeAddr), regFile_18, _GEN_17) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_19 = mux(eq(UInt<5>("h13"), io_writeAddr), regFile_19, _GEN_18) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_20 = mux(eq(UInt<5>("h14"), io_writeAddr), regFile_20, _GEN_19) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_21 = mux(eq(UInt<5>("h15"), io_writeAddr), regFile_21, _GEN_20) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_22 = mux(eq(UInt<5>("h16"), io_writeAddr), regFile_22, _GEN_21) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_23 = mux(eq(UInt<5>("h17"), io_writeAddr), regFile_23, _GEN_22) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_24 = mux(eq(UInt<5>("h18"), io_writeAddr), regFile_24, _GEN_23) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_25 = mux(eq(UInt<5>("h19"), io_writeAddr), regFile_25, _GEN_24) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_26 = mux(eq(UInt<5>("h1a"), io_writeAddr), regFile_26, _GEN_25) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_27 = mux(eq(UInt<5>("h1b"), io_writeAddr), regFile_27, _GEN_26) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_28 = mux(eq(UInt<5>("h1c"), io_writeAddr), regFile_28, _GEN_27) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_29 = mux(eq(UInt<5>("h1d"), io_writeAddr), regFile_29, _GEN_28) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_30 = mux(eq(UInt<5>("h1e"), io_writeAddr), regFile_30, _GEN_29) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _GEN_31 = mux(eq(UInt<5>("h1f"), io_writeAddr), regFile_31, _GEN_30) @[core/src/main/scala/Main.scala 21:{31,31}]
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node _regFile_io_writeAddr = _GEN_31 @[core/src/main/scala/Main.scala 21:31]
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node _regFile_T = mux(io_writeEnable, io_writeData, _regFile_io_writeAddr) @[core/src/main/scala/Main.scala 21:31]
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node _regFile_io_writeAddr_0 = _regFile_T @[core/src/main/scala/Main.scala 21:{25,25}]
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node _GEN_32 = mux(eq(UInt<1>("h0"), io_writeAddr), _regFile_io_writeAddr_0, regFile_0) @[core/src/main/scala/Main.scala 17:24 21:{25,25}]
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node _GEN_33 = mux(eq(UInt<1>("h1"), io_writeAddr), _regFile_io_writeAddr_0, regFile_1) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_34 = mux(eq(UInt<2>("h2"), io_writeAddr), _regFile_io_writeAddr_0, regFile_2) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_35 = mux(eq(UInt<2>("h3"), io_writeAddr), _regFile_io_writeAddr_0, regFile_3) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_36 = mux(eq(UInt<3>("h4"), io_writeAddr), _regFile_io_writeAddr_0, regFile_4) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_37 = mux(eq(UInt<3>("h5"), io_writeAddr), _regFile_io_writeAddr_0, regFile_5) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_38 = mux(eq(UInt<3>("h6"), io_writeAddr), _regFile_io_writeAddr_0, regFile_6) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_39 = mux(eq(UInt<3>("h7"), io_writeAddr), _regFile_io_writeAddr_0, regFile_7) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_40 = mux(eq(UInt<4>("h8"), io_writeAddr), _regFile_io_writeAddr_0, regFile_8) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_41 = mux(eq(UInt<4>("h9"), io_writeAddr), _regFile_io_writeAddr_0, regFile_9) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_42 = mux(eq(UInt<4>("ha"), io_writeAddr), _regFile_io_writeAddr_0, regFile_10) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_43 = mux(eq(UInt<4>("hb"), io_writeAddr), _regFile_io_writeAddr_0, regFile_11) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_44 = mux(eq(UInt<4>("hc"), io_writeAddr), _regFile_io_writeAddr_0, regFile_12) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_45 = mux(eq(UInt<4>("hd"), io_writeAddr), _regFile_io_writeAddr_0, regFile_13) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_46 = mux(eq(UInt<4>("he"), io_writeAddr), _regFile_io_writeAddr_0, regFile_14) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_47 = mux(eq(UInt<4>("hf"), io_writeAddr), _regFile_io_writeAddr_0, regFile_15) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_48 = mux(eq(UInt<5>("h10"), io_writeAddr), _regFile_io_writeAddr_0, regFile_16) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_49 = mux(eq(UInt<5>("h11"), io_writeAddr), _regFile_io_writeAddr_0, regFile_17) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_50 = mux(eq(UInt<5>("h12"), io_writeAddr), _regFile_io_writeAddr_0, regFile_18) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_51 = mux(eq(UInt<5>("h13"), io_writeAddr), _regFile_io_writeAddr_0, regFile_19) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_52 = mux(eq(UInt<5>("h14"), io_writeAddr), _regFile_io_writeAddr_0, regFile_20) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_53 = mux(eq(UInt<5>("h15"), io_writeAddr), _regFile_io_writeAddr_0, regFile_21) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_54 = mux(eq(UInt<5>("h16"), io_writeAddr), _regFile_io_writeAddr_0, regFile_22) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_55 = mux(eq(UInt<5>("h17"), io_writeAddr), _regFile_io_writeAddr_0, regFile_23) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_56 = mux(eq(UInt<5>("h18"), io_writeAddr), _regFile_io_writeAddr_0, regFile_24) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_57 = mux(eq(UInt<5>("h19"), io_writeAddr), _regFile_io_writeAddr_0, regFile_25) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_58 = mux(eq(UInt<5>("h1a"), io_writeAddr), _regFile_io_writeAddr_0, regFile_26) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_59 = mux(eq(UInt<5>("h1b"), io_writeAddr), _regFile_io_writeAddr_0, regFile_27) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_60 = mux(eq(UInt<5>("h1c"), io_writeAddr), _regFile_io_writeAddr_0, regFile_28) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_61 = mux(eq(UInt<5>("h1d"), io_writeAddr), _regFile_io_writeAddr_0, regFile_29) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_62 = mux(eq(UInt<5>("h1e"), io_writeAddr), _regFile_io_writeAddr_0, regFile_30) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_63 = mux(eq(UInt<5>("h1f"), io_writeAddr), _regFile_io_writeAddr_0, regFile_31) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
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node _GEN_64 = validif(eq(UInt<1>("h0"), io_readAddr_0), regFile_0) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_65 = mux(eq(UInt<1>("h1"), io_readAddr_0), regFile_1, _GEN_64) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_66 = mux(eq(UInt<2>("h2"), io_readAddr_0), regFile_2, _GEN_65) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_67 = mux(eq(UInt<2>("h3"), io_readAddr_0), regFile_3, _GEN_66) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_68 = mux(eq(UInt<3>("h4"), io_readAddr_0), regFile_4, _GEN_67) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_69 = mux(eq(UInt<3>("h5"), io_readAddr_0), regFile_5, _GEN_68) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_70 = mux(eq(UInt<3>("h6"), io_readAddr_0), regFile_6, _GEN_69) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_71 = mux(eq(UInt<3>("h7"), io_readAddr_0), regFile_7, _GEN_70) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_72 = mux(eq(UInt<4>("h8"), io_readAddr_0), regFile_8, _GEN_71) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_73 = mux(eq(UInt<4>("h9"), io_readAddr_0), regFile_9, _GEN_72) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_74 = mux(eq(UInt<4>("ha"), io_readAddr_0), regFile_10, _GEN_73) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_75 = mux(eq(UInt<4>("hb"), io_readAddr_0), regFile_11, _GEN_74) @[core/src/main/scala/Main.scala 25:{20,20}]
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node _GEN_76 = mux(eq(UInt<4>("hc"), io_readAddr_0), regFile_12, _GEN_75) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_77 = mux(eq(UInt<4>("hd"), io_readAddr_0), regFile_13, _GEN_76) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_78 = mux(eq(UInt<4>("he"), io_readAddr_0), regFile_14, _GEN_77) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_79 = mux(eq(UInt<4>("hf"), io_readAddr_0), regFile_15, _GEN_78) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_80 = mux(eq(UInt<5>("h10"), io_readAddr_0), regFile_16, _GEN_79) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_81 = mux(eq(UInt<5>("h11"), io_readAddr_0), regFile_17, _GEN_80) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_82 = mux(eq(UInt<5>("h12"), io_readAddr_0), regFile_18, _GEN_81) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_83 = mux(eq(UInt<5>("h13"), io_readAddr_0), regFile_19, _GEN_82) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_84 = mux(eq(UInt<5>("h14"), io_readAddr_0), regFile_20, _GEN_83) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_85 = mux(eq(UInt<5>("h15"), io_readAddr_0), regFile_21, _GEN_84) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_86 = mux(eq(UInt<5>("h16"), io_readAddr_0), regFile_22, _GEN_85) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_87 = mux(eq(UInt<5>("h17"), io_readAddr_0), regFile_23, _GEN_86) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_88 = mux(eq(UInt<5>("h18"), io_readAddr_0), regFile_24, _GEN_87) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_89 = mux(eq(UInt<5>("h19"), io_readAddr_0), regFile_25, _GEN_88) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_90 = mux(eq(UInt<5>("h1a"), io_readAddr_0), regFile_26, _GEN_89) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_91 = mux(eq(UInt<5>("h1b"), io_readAddr_0), regFile_27, _GEN_90) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_92 = mux(eq(UInt<5>("h1c"), io_readAddr_0), regFile_28, _GEN_91) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_93 = mux(eq(UInt<5>("h1d"), io_readAddr_0), regFile_29, _GEN_92) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_94 = mux(eq(UInt<5>("h1e"), io_readAddr_0), regFile_30, _GEN_93) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_95 = mux(eq(UInt<5>("h1f"), io_readAddr_0), regFile_31, _GEN_94) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_96 = validif(eq(UInt<1>("h0"), io_readAddr_1), regFile_0) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_97 = mux(eq(UInt<1>("h1"), io_readAddr_1), regFile_1, _GEN_96) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_98 = mux(eq(UInt<2>("h2"), io_readAddr_1), regFile_2, _GEN_97) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_99 = mux(eq(UInt<2>("h3"), io_readAddr_1), regFile_3, _GEN_98) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_100 = mux(eq(UInt<3>("h4"), io_readAddr_1), regFile_4, _GEN_99) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_101 = mux(eq(UInt<3>("h5"), io_readAddr_1), regFile_5, _GEN_100) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_102 = mux(eq(UInt<3>("h6"), io_readAddr_1), regFile_6, _GEN_101) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_103 = mux(eq(UInt<3>("h7"), io_readAddr_1), regFile_7, _GEN_102) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_104 = mux(eq(UInt<4>("h8"), io_readAddr_1), regFile_8, _GEN_103) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_105 = mux(eq(UInt<4>("h9"), io_readAddr_1), regFile_9, _GEN_104) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_106 = mux(eq(UInt<4>("ha"), io_readAddr_1), regFile_10, _GEN_105) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_107 = mux(eq(UInt<4>("hb"), io_readAddr_1), regFile_11, _GEN_106) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_108 = mux(eq(UInt<4>("hc"), io_readAddr_1), regFile_12, _GEN_107) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_109 = mux(eq(UInt<4>("hd"), io_readAddr_1), regFile_13, _GEN_108) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_110 = mux(eq(UInt<4>("he"), io_readAddr_1), regFile_14, _GEN_109) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_111 = mux(eq(UInt<4>("hf"), io_readAddr_1), regFile_15, _GEN_110) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_112 = mux(eq(UInt<5>("h10"), io_readAddr_1), regFile_16, _GEN_111) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_113 = mux(eq(UInt<5>("h11"), io_readAddr_1), regFile_17, _GEN_112) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_114 = mux(eq(UInt<5>("h12"), io_readAddr_1), regFile_18, _GEN_113) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_115 = mux(eq(UInt<5>("h13"), io_readAddr_1), regFile_19, _GEN_114) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_116 = mux(eq(UInt<5>("h14"), io_readAddr_1), regFile_20, _GEN_115) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_117 = mux(eq(UInt<5>("h15"), io_readAddr_1), regFile_21, _GEN_116) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_118 = mux(eq(UInt<5>("h16"), io_readAddr_1), regFile_22, _GEN_117) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_119 = mux(eq(UInt<5>("h17"), io_readAddr_1), regFile_23, _GEN_118) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_120 = mux(eq(UInt<5>("h18"), io_readAddr_1), regFile_24, _GEN_119) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_121 = mux(eq(UInt<5>("h19"), io_readAddr_1), regFile_25, _GEN_120) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_122 = mux(eq(UInt<5>("h1a"), io_readAddr_1), regFile_26, _GEN_121) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_123 = mux(eq(UInt<5>("h1b"), io_readAddr_1), regFile_27, _GEN_122) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_124 = mux(eq(UInt<5>("h1c"), io_readAddr_1), regFile_28, _GEN_123) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_125 = mux(eq(UInt<5>("h1d"), io_readAddr_1), regFile_29, _GEN_124) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_126 = mux(eq(UInt<5>("h1e"), io_readAddr_1), regFile_30, _GEN_125) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_127 = mux(eq(UInt<5>("h1f"), io_readAddr_1), regFile_31, _GEN_126) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _regFile_WIRE_0 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_1 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_2 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_3 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_4 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_5 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_6 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_7 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_8 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_9 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_10 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_11 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_12 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_13 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_14 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_15 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_16 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_17 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_18 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_19 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_20 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_21 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_22 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_23 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_24 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_25 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_26 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_27 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_28 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_29 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_30 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_31 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_io_readAddr_0 = _GEN_95 @[core/src/main/scala/Main.scala 25:20]
|
||||
node _regFile_io_readAddr_1 = _GEN_127 @[core/src/main/scala/Main.scala 25:20]
|
||||
io_readData_0 <= _regFile_io_readAddr_0 @[core/src/main/scala/Main.scala 25:20]
|
||||
io_readData_1 <= _regFile_io_readAddr_1 @[core/src/main/scala/Main.scala 25:20]
|
||||
regFile_0 <= mux(reset, _regFile_WIRE_0, UInt<1>("h0")) @[core/src/main/scala/Main.scala 17:{24,24} 22:14]
|
||||
regFile_1 <= mux(reset, _regFile_WIRE_1, _GEN_33) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_2 <= mux(reset, _regFile_WIRE_2, _GEN_34) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_3 <= mux(reset, _regFile_WIRE_3, _GEN_35) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_4 <= mux(reset, _regFile_WIRE_4, _GEN_36) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_5 <= mux(reset, _regFile_WIRE_5, _GEN_37) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_6 <= mux(reset, _regFile_WIRE_6, _GEN_38) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_7 <= mux(reset, _regFile_WIRE_7, _GEN_39) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_8 <= mux(reset, _regFile_WIRE_8, _GEN_40) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_9 <= mux(reset, _regFile_WIRE_9, _GEN_41) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_10 <= mux(reset, _regFile_WIRE_10, _GEN_42) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_11 <= mux(reset, _regFile_WIRE_11, _GEN_43) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_12 <= mux(reset, _regFile_WIRE_12, _GEN_44) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_13 <= mux(reset, _regFile_WIRE_13, _GEN_45) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_14 <= mux(reset, _regFile_WIRE_14, _GEN_46) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_15 <= mux(reset, _regFile_WIRE_15, _GEN_47) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_16 <= mux(reset, _regFile_WIRE_16, _GEN_48) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_17 <= mux(reset, _regFile_WIRE_17, _GEN_49) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_18 <= mux(reset, _regFile_WIRE_18, _GEN_50) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_19 <= mux(reset, _regFile_WIRE_19, _GEN_51) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_20 <= mux(reset, _regFile_WIRE_20, _GEN_52) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_21 <= mux(reset, _regFile_WIRE_21, _GEN_53) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_22 <= mux(reset, _regFile_WIRE_22, _GEN_54) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_23 <= mux(reset, _regFile_WIRE_23, _GEN_55) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_24 <= mux(reset, _regFile_WIRE_24, _GEN_56) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_25 <= mux(reset, _regFile_WIRE_25, _GEN_57) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_26 <= mux(reset, _regFile_WIRE_26, _GEN_58) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_27 <= mux(reset, _regFile_WIRE_27, _GEN_59) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_28 <= mux(reset, _regFile_WIRE_28, _GEN_60) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_29 <= mux(reset, _regFile_WIRE_29, _GEN_61) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_30 <= mux(reset, _regFile_WIRE_30, _GEN_62) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_31 <= mux(reset, _regFile_WIRE_31, _GEN_63) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
Loading…
Reference in a new issue