From dc03efa59cfc780bfb5e03cfc756813c89c56c53 Mon Sep 17 00:00:00 2001 From: tracer-ysyx Date: Tue, 26 Mar 2024 01:48:27 +0800 Subject: [PATCH] =?UTF-8?q?>=20compile=20NEMU=20ysyx=5F22040000=20?= =?UTF-8?q?=E6=9D=8E=E5=BF=83=E6=9D=A8=20Linux=20calcite=206.6.19=20#1-Nix?= =?UTF-8?q?OS=20SMP=20PREEMPT=5FDYNAMIC=20Fri=20Mar=20=201=2012:35:11=20UT?= =?UTF-8?q?C=202024=20x86=5F64=20GNU/Linux=20=2001:48:27=20=20up=20=2011:2?= =?UTF-8?q?4,=20=202=20users,=20=20load=20average:=200.73,=200.41,=200.39?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- nemu/src/isa/riscv32/difftest/dut.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nemu/src/isa/riscv32/difftest/dut.c b/nemu/src/isa/riscv32/difftest/dut.c index c5ebf13..d6dd6f5 100644 --- a/nemu/src/isa/riscv32/difftest/dut.c +++ b/nemu/src/isa/riscv32/difftest/dut.c @@ -18,6 +18,9 @@ #include "../local-include/reg.h" bool isa_difftest_checkregs(CPU_state *ref_r, vaddr_t pc) { + for(int i = 0; i < MUXDEF(CONFIG_RVE, 16, 32); i++) { + difftest_check_reg(reg_name(i), pc, ref_r->gpr[i], gpr(i)); + } return false; }