> sim RTL

ysyx_22040000 李心杨
Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
 14:36:38  up  23:15,  2 users,  load average: 1.36, 1.54, 1.31
This commit is contained in:
tracer-ysyx 2024-01-01 14:36:38 +08:00 committed by xinyangli
parent aa62c3b7b7
commit d9a1e124e8

View file

@ -10,15 +10,7 @@ SUBMAKE := $(OBJDIR)/Vexample.mk
VERILATOR_FLAGS := --cc --exe
LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image
all: sim
sim-bin: VERILATOR_FLAGS += --trace
sim-bin: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample git_trace
sim: sim-bin
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================"
@$(OBJDIR)/Vexample
all: sim-bin nvboard-bin
$(OBJDIR)/Vexample: $(SUBMAKE)
$(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample
@ -29,17 +21,8 @@ $(SUBMAKE): $(VSRC) $(CPPSRCS) $(OBJDIR)
$(OBJDIR):
mkdir -p $(OBJDIR)
ifneq (,$(wildcard ../Makefile))
include ../Makefile
else
define git_commit # not in ICS subfolder, no tracing
endef
endif
git_trace:
$(call git_commit, "sim RTL")
.PHONY: clean nvboard compile_commands.json
sim-bin: VERILATOR_FLAGS += --trace
sim-bin: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample
SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
NXDC_FILES := $(abspath constr/top.nxdc)
@ -54,9 +37,30 @@ nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags)
nvboard-bin: $(VSRC) $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/Vexample
nvboard: nvboard-bin
ifneq (,$(wildcard ../Makefile))
include ../Makefile
else
define git_commit # not in ICS subfolder, no tracing
endef
endif
git_trace_sim:
$(call git_commit, "sim RTL")
git_trace_nvboard:
$(call git_commit, "nvboard")
.PHONY: clean nvboard sim compile_commands.json
nvboard: nvboard-bin git_trace_nvboard
@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/Vexample
sim: sim-bin git_trace_sim
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================"
@$(OBJDIR)/Vexample
compile_commands.json: clean
bear --output nvboard.json -- $(MAKE) nvboard-bin