> sim RTL
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 14:36:38 up 23:15, 2 users, load average: 1.36, 1.54, 1.31
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commit
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1 changed files with 25 additions and 21 deletions
46
npc/Makefile
46
npc/Makefile
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@ -10,15 +10,7 @@ SUBMAKE := $(OBJDIR)/Vexample.mk
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VERILATOR_FLAGS := --cc --exe
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LDFLAGS += $(shell sdl2-config --libs) -lSDL2_image
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all: sim
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sim-bin: VERILATOR_FLAGS += --trace
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sim-bin: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample git_trace
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sim: sim-bin
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@echo "Running" $(OBJDIR)/Vexample "..."
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@echo "================================"
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@$(OBJDIR)/Vexample
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all: sim-bin nvboard-bin
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$(OBJDIR)/Vexample: $(SUBMAKE)
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$(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample
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@ -29,17 +21,8 @@ $(SUBMAKE): $(VSRC) $(CPPSRCS) $(OBJDIR)
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$(OBJDIR):
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mkdir -p $(OBJDIR)
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ifneq (,$(wildcard ../Makefile))
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include ../Makefile
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else
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define git_commit # not in ICS subfolder, no tracing
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endef
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endif
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git_trace:
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$(call git_commit, "sim RTL")
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.PHONY: clean nvboard compile_commands.json
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sim-bin: VERILATOR_FLAGS += --trace
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sim-bin: $(VSRC) $(CPPSRCS) $(OBJDIR)/Vexample
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SRC_AUTO_BIND := $(abspath $(PREFIX)/auto_bind.cpp)
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NXDC_FILES := $(abspath constr/top.nxdc)
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@ -54,9 +37,30 @@ nvboard-bin: CXXFLAGS += -I$(NVBOARD_HOME)/include $(shell sdl2-config --cflags)
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nvboard-bin: $(VSRC) $(CPPSRCS) $(SUBMAKE) $(SRC_AUTO_BIND) $(OBJDIR)/Vexample
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nvboard: nvboard-bin
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ifneq (,$(wildcard ../Makefile))
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include ../Makefile
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else
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define git_commit # not in ICS subfolder, no tracing
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endef
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endif
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git_trace_sim:
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$(call git_commit, "sim RTL")
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git_trace_nvboard:
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$(call git_commit, "nvboard")
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.PHONY: clean nvboard sim compile_commands.json
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nvboard: nvboard-bin git_trace_nvboard
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@NVBOARD_HOME=$(NVBOARD_HOME) $(OBJDIR)/Vexample
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sim: sim-bin git_trace_sim
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@echo "Running" $(OBJDIR)/Vexample "..."
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@echo "================================"
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@$(OBJDIR)/Vexample
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compile_commands.json: clean
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bear --output nvboard.json -- $(MAKE) nvboard-bin
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