From d4ab3e5752c30243fc711d3621dec507281b252f Mon Sep 17 00:00:00 2001
From: tracer-ysyx <tracer@ysyx.org>
Date: Sat, 6 Jan 2024 13:21:08 +0800
Subject: [PATCH] =?UTF-8?q?>=20configure(npc)=20=20ysyx=5F22040000=20?=
 =?UTF-8?q?=E6=9D=8E=E5=BF=83=E6=9D=A8=20=20Linux=20calcite=206.1.69=20#1-?=
 =?UTF-8?q?NixOS=20SMP=20PREEMPT=5FDYNAMIC=20Wed=20Dec=2020=2016:00:29=20U?=
 =?UTF-8?q?TC=202023=20x86=5F64=20GNU/Linux=20=20=2013:21:08=20=20up=201?=
 =?UTF-8?q?=20day=2022:07,=20=202=20users,=20=20load=20average:=200.94,=20?=
 =?UTF-8?q?1.60,=201.63?=
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---
 npc/core/src/main/scala/Main.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index 8f9e58a..cef022a 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -44,7 +44,7 @@ class ALUGenerator(width: Int) extends Module {
   val slt = io.a < io.b
   val eq = io.a === io.b
 
-  io.out := MuxLookup(0.U, io.op, Seq(
+  io.out := MuxLookup(io.op, 0.U) Map(
     0.U -> add,
     1.U -> add, // add with b reversed
     2.U -> not,
@@ -53,7 +53,7 @@ class ALUGenerator(width: Int) extends Module {
     5.U -> xor,
     6.U -> slt,
     7.U -> eq,
-  ))
+  )
 }
 
 class MuxGenerator(width: Int, nInput: Int) extends Module {