> sim RTL
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 11:09:46 up 19:48, 2 users, load average: 0.84, 0.64, 0.85
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parent
88a55f87ea
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4 changed files with 19 additions and 33 deletions
1
.gitignore
vendored
1
.gitignore
vendored
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@ -11,3 +11,4 @@
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!.gitignore
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!.gitignore
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!init.sh
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!init.sh
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/fceux-am
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/fceux-am
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/nvboard
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12
npc/Makefile
12
npc/Makefile
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@ -1,9 +1,13 @@
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VSRC := $(wildcard vsrc/*.v)
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VSRC := $(wildcard vsrc/*.v)
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CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
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CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
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CPPSRC += $(SRC_AUTO_BIND)
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NXDC_FILES = $(abspath constr/top.nxdc)
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PREFIX ?= build
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PREFIX ?= build
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OBJDIR := $(PREFIX)/obj
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OBJDIR := $(PREFIX)/obj
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SUBMAKE := $(OBJDIR)/Vexample.mk
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SUBMAKE := $(OBJDIR)/Vexample.mk
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VERILATOR_FLAGS := --cc --exe
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VERILATOR_FLAGS := --cc --exe
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NVBOARD_HOME ?= $(abspath ../nvboard)
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all: sim
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all: sim
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@ -18,11 +22,17 @@ $(OBJDIR)/Vexample: $(SUBMAKE)
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$(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample
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$(MAKE) -C $(OBJDIR) -f $(notdir $(SUBMAKE)) Vexample
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$(SUBMAKE): $(VSRC) $(CPPSRC) $(OBJDIR)
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$(SUBMAKE): $(VSRC) $(CPPSRC) $(OBJDIR)
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verilator $(VERILATOR_FLAGS) --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
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verilator $(VERILATOR_FLAGS) \
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--Mdir $(abspath $(OBJDIR)) $(VSRC) $(CPPSRC)
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# $(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) \
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$(OBJDIR):
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$(OBJDIR):
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mkdir -p $(OBJDIR)
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mkdir -p $(OBJDIR)
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SRC_AUTO_BIND = $(abspath $(PREFIX)/auto_bind.cpp)
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$(SRC_AUTO_BIND): $(NXDC_FILES)
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python3 $(NVBOARD_HOME)/scripts/auto_pin_bind.py $^ $@
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include ../Makefile
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include ../Makefile
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.PHONY: clean
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.PHONY: clean
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@ -14,7 +14,14 @@
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gtkwave
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gtkwave
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gcc
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gcc
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bear
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bear
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clang-tools
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rnix-lsp
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];
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];
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nativeBuildInputs = with pkgs; [
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python3
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];
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shellHook = ''
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shellHook = ''
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export NEMU_HOME=/home/xin/repo/ysyx-workbench/nemu
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export NEMU_HOME=/home/xin/repo/ysyx-workbench/nemu
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'';
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'';
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@ -1,32 +0,0 @@
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#include "verilated_vcd_c.h"
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#include "Vexample.h"
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#include "verilated.h"
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int main(int argc, char **argv, char **env) {
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}
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int main(int argc, char **argv, char **env) {
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Verilated::commandArgs(argc, argv);
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Verilated::traceEverOn(true);
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VerilatedVcdC* tfp = new VerilatedVcdC;
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Vexample *top = new Vexample;
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int round = 100;
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while (round--) {
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int a = rand() & 1;
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int b = rand() & 1;
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top->a = a;
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top->b = b;
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top->eval();
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printf("a = %d, b = %d, f = %d\n", a, b, top->f);
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assert(top->f == (a ^ b));
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}
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exit(0);
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topp->trace (tfp, 99);
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tfp->open ("obj_dir/t_trace_ena_cc/simx.vcd");
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...
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while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
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main_time += #;
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tfp->dump (main_time);
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}
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tfp->close();
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}
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