> trace RTL

ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 20:12:41  up  23:10,  2 users,  load average: 0.26, 0.52, 0.57
This commit is contained in:
tracer-ysyx 2023-12-23 20:12:41 +08:00 committed by xinyangli
parent 702116d8ad
commit ceb06fd70c

View file

@ -2,22 +2,24 @@ VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp)) CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
PREFIX ?= build PREFIX ?= build
OBJDIR := $(PREFIX)/obj OBJDIR := $(PREFIX)/obj
SUBMAKE := $(OBJDIR)/Vexample.mk
VERILATOR_FLAGS := --cc --exe VERILATOR_FLAGS := --cc --exe
all: $(OBJDIR) all: sim
$(MAKE) -j -C $(OBJDIR) -f Vexample.mk Vexample
sim: $(OBJDIR) $(VSRC) $(CPPSRC) sim: $(OBJDIR) $(VSRC) $(CPPSRC) $(SUBMAKE)
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!! $(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Running" $(OBJDIR)/Vexample "..." @echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================" @echo "================================"
@$(OBJDIR)/Vexample +tracing_off @$(OBJDIR)/Vexample
trace: VERILATOR_FLAGS += --trace trace: VERILATOR_FLAGS += --trace
trace: $(OBJDIR) $(VSRC) $(CPPSRC) trace: $(OBJDIR) $(VSRC) $(CPPSRC) $(SUBMAKE)
$(call git_commit, "trace RTL") # DO NOT REMOVE THIS LINE!!! $(call git_commit, "trace RTL") # DO NOT REMOVE THIS LINE!!!
@$(OBJDIR)/Vexample @$(OBJDIR)/Vexample
$(SUBMAKE): $(VSRC) $(CPPSRC)
verilator $(VERILATOR_FLAGS) --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
$(OBJDIR): $(VSRC) $(CPPSRC) $(OBJDIR): $(VSRC) $(CPPSRC)
mkdir -p $(OBJDIR) mkdir -p $(OBJDIR)