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> trace RTL

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ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 20:11:04  up  23:09,  2 users,  load average: 0.52, 0.64, 0.62
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tracer-ysyx 2023-12-23 20:11:04 +08:00 committed by xinyangli
parent a1624036d1
commit cdf6ff8030
1 changed files with 2 additions and 2 deletions
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4
npc/Makefile
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@ -7,14 +7,14 @@ VERILATOR_FLAGS := --cc --exe
all: $(OBJDIR)
$(MAKE) -j -C $(OBJDIR) -f Vexample.mk Vexample
sim: all
sim: $(OBJDIR) $(VSRC) $(CPPSRC)
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================"
@$(OBJDIR)/Vexample +tracing_off
trace: VERILATOR_FLAGS += --trace
trace: all
trace: $(OBJDIR) $(VSRC) $(CPPSRC)
$(call git_commit, "trace RTL") # DO NOT REMOVE THIS LINE!!!
@$(OBJDIR)/Vexample