From cbff32c35c94409a021b76a6e8b60a11aefb6be7 Mon Sep 17 00:00:00 2001 From: tracer-ysyx Date: Wed, 10 Jan 2024 21:25:48 +0800 Subject: [PATCH] =?UTF-8?q?>=20configure(npc)=20=20ysyx=5F22040000=20?= =?UTF-8?q?=E6=9D=8E=E5=BF=83=E6=9D=A8=20=20Linux=20calcite=206.1.69=20#1-?= =?UTF-8?q?NixOS=20SMP=20PREEMPT=5FDYNAMIC=20Wed=20Dec=2020=2016:00:29=20U?= =?UTF-8?q?TC=202023=20x86=5F64=20GNU/Linux=20=20=2021:25:48=20=20up=202?= =?UTF-8?q?=20days=2020:26,=20=202=20users,=20=20load=20average:=201.07,?= =?UTF-8?q?=201.30,=201.00?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- npc/core/src/main/scala/Keyboard.scala | 43 +++++++++++++ npc/core/src/main/scala/Main.scala | 6 +- .../main/scala/SegControllerGenerator.scala | 31 ++++++++++ npc/core/src/main/scala/SegGenerator.scala | 62 ------------------- 4 files changed, 77 insertions(+), 65 deletions(-) create mode 100644 npc/core/src/main/scala/SegControllerGenerator.scala delete mode 100644 npc/core/src/main/scala/SegGenerator.scala diff --git a/npc/core/src/main/scala/Keyboard.scala b/npc/core/src/main/scala/Keyboard.scala index ddc512c..60c65c5 100644 --- a/npc/core/src/main/scala/Keyboard.scala +++ b/npc/core/src/main/scala/Keyboard.scala @@ -53,3 +53,46 @@ class KeyboardController extends Module { received := false.B } } + +class KeyboardSegController extends Module { + val io = IO(new Bundle{ + val keycode = Flipped(Decoupled(UInt(8.W))) + val segs = Vec(8, UInt(8.W)) + }) + io.keycode.ready := false.B + when(io.keycode.valid) { + io.keycode.ready := true.B + } + + val keycode_to_ascii = Seq( + 0x1C.U, 0x32.U, 0x21.U, 0x23.U, 0x24.U, 0x2B.U, + 0x34.U, 0x33.U, 0x43.U, 0x3B.U, 0x42.U, 0x4B.U, + 0x3A.U, 0x31.U, 0x44.U, 0x4D.U, 0x15.U, 0x2D.U, + 0x1B.U, 0x2C.U, 0x3C.U, 0x2A.U, 0x1D.U, 0x22.U, + 0x35.U, 0x1A.U, 0x45.U, 0x16.U, 0x1E.U, 0x26.U, + 0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U, + ).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U)) + + val keycode = RegInit(0.U(8.W)) + val counter = Counter(0xFF) + val release_state = RegInit(Bool(), false.B) + when(io.keycode.ready && io.keycode.valid) { + when(io.keycode.bits === 0xF0.U) { + release_state := true.B + }.elsewhen(!release_state) { + keycode := io.keycode.bits + counter.inc() + }.otherwise{ + // Release code on io.keycode.bits + release_state := false.B + } + } + + val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4)) + val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii) + + val seg_contoller = SegControllerGenerator(8) + + seg_contoller.io.in_segs := VecInit(Seq(keycode, ascii, counter.value, 0.U)) + io.segs := seg_contoller.io.segs +} diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala index 5644090..c06bc8e 100644 --- a/npc/core/src/main/scala/Main.scala +++ b/npc/core/src/main/scala/Main.scala @@ -3,6 +3,7 @@ package npc import chisel3._ import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse} import chisel3.stage.ChiselOption +import npc.util.KeyboardSegController class Switch extends Module { val io = IO(new Bundle { @@ -13,7 +14,7 @@ class Switch extends Module { io.out := io.sw(0) ^ io.sw(1) } -import npc.util.{PS2Port, KeyboardController, SegGenerator} +import npc.util.{PS2Port, KeyboardController, SegControllerGenerator} class Keyboard extends Module { val io = IO(new Bundle { @@ -21,7 +22,7 @@ class Keyboard extends Module { val segs = Output(Vec(8, UInt(8.W))) }) - val seg_handler = Module(new SegGenerator(seg_count = 8)) + val seg_handler = Module(new KeyboardSegController) val keyboard_controller = Module(new KeyboardController) seg_handler.io.keycode <> keyboard_controller.io.out @@ -30,4 +31,3 @@ class Keyboard extends Module { io.segs := seg_handler.io.segs } -class SegHandler extends SegGenerator(8) { } diff --git a/npc/core/src/main/scala/SegControllerGenerator.scala b/npc/core/src/main/scala/SegControllerGenerator.scala new file mode 100644 index 0000000..49f05d3 --- /dev/null +++ b/npc/core/src/main/scala/SegControllerGenerator.scala @@ -0,0 +1,31 @@ +package npc.util + +import chisel3._ +import chisel3.util._ +import chisel3.util.log2Ceil + +class SegControllerGenerator(seg_count: Int) extends Module { + val io = IO(new Bundle { + val in_segs = Input(Vec(seg_count, UInt())) + val segs = Output(Vec(seg_count, UInt(8.W))) + }) + val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq( + "b00000011".U, "b10011111".U, "b00100101".U, "b00001101".U, + "b10011001".U, "b01001001".U, "b01000001".U, "b00011111".U, + "b00000001".U, "b00001001".U, "b00010001".U, "b11000001".U, + "b01100011".U, "b10000101".U, "b01100001".U, "b01110001".U, + )) + val vec_size = (io.in_segs.getWidth + 3) / 4 + val vec = io.in_segs.asTypeOf(Vec(vec_size, UInt(4.W))) + + val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(8.W)))) + seg_regs := vec.map(MuxLookup(_, 0xFF.U)(digit_to_seg)) ++ Seq(0xFF.U, 0xFF.U) + + io.segs := seg_regs +} + +object SegControllerGenerator { + def apply(seg_count: Int): SegControllerGenerator = { + new SegControllerGenerator(seg_count) + } +} diff --git a/npc/core/src/main/scala/SegGenerator.scala b/npc/core/src/main/scala/SegGenerator.scala deleted file mode 100644 index 56e65b8..0000000 --- a/npc/core/src/main/scala/SegGenerator.scala +++ /dev/null @@ -1,62 +0,0 @@ -package npc.util - -import chisel3._ -import chisel3.util._ -import chisel3.util.log2Ceil - -class SegGenerator(seg_count: Int) extends Module { - val io = IO(new Bundle { - val keycode = Flipped(Decoupled(UInt(8.W))) - val segs = Output(Vec(seg_count, UInt(8.W))) - }) - io.keycode.ready := false.B - when(io.keycode.valid) { - io.keycode.ready := true.B - } - - val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(8.W)))) - val last_keycode = RegInit(0.U(8.W)) - val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq( - "b00000011".U, "b10011111".U, "b00100101".U, "b00001101".U, - "b10011001".U, "b01001001".U, "b01000001".U, "b00011111".U, - "b00000001".U, "b00001001".U, "b00010001".U, "b11000001".U, - "b01100011".U, "b10000101".U, "b01100001".U, "b01110001".U, - )) - - val keycode_to_ascii = Seq( - 0x1C.U, 0x32.U, 0x21.U, 0x23.U, 0x24.U, 0x2B.U, - 0x34.U, 0x33.U, 0x43.U, 0x3B.U, 0x42.U, 0x4B.U, - 0x3A.U, 0x31.U, 0x44.U, 0x4D.U, 0x15.U, 0x2D.U, - 0x1B.U, 0x2C.U, 0x3C.U, 0x2A.U, 0x1D.U, 0x22.U, - 0x35.U, 0x1A.U, 0x45.U, 0x16.U, 0x1E.U, 0x26.U, - 0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U, - ).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U)) - - val keycode = RegInit(0.U(8.W)) - val counter = Counter(0xFF) - val release_state = RegInit(Bool(), false.B) - when(io.keycode.ready && io.keycode.valid) { - when(io.keycode.bits === 0xF0.U) { - release_state := true.B - }.elsewhen(!release_state) { - keycode := io.keycode.bits - counter.inc() - }.otherwise{ - // Release code on io.keycode.bits - release_state := false.B - } - } - - val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4)) - val keycode_seg = keycode_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg)) - - val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii) - val ascii_digits = VecInit(ascii(3,0)) ++ VecInit(ascii(6,4)) - val ascii_seg = ascii_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg)) - - val count_digits = VecInit(counter.value(3,0)) ++ VecInit(counter.value(7,4)) - val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg)) - seg_regs := keycode_seg ++ ascii_seg ++ count_seg ++ Seq(0xFF.U, 0xFF.U) - - io.segs := seg_regs -}