From ba18436c6c9cd4b793a5a52c643ef6641a9f3913 Mon Sep 17 00:00:00 2001 From: xinyangli Date: Fri, 9 Aug 2024 19:58:10 +0800 Subject: [PATCH] npc,chore: reformat scala code --- .scalafmt.conf | 2 + flake.nix | 7 + npc/core/build.sbt | 17 +- npc/core/src/main/scala/components/Mem.scala | 3 +- .../scala/components/ProgramCounter.scala | 6 +- .../main/scala/components/RegisterFile.scala | 10 +- npc/core/src/main/scala/top/ArgParse.scala | 21 +- npc/core/src/main/scala/top/Config.scala | 14 +- npc/core/src/main/scala/top/FlowMain.scala | 444 +++++++++++------- npc/core/src/main/scala/top/Main.scala | 57 ++- npc/core/src/main/scala/utils/Keyboard.scala | 54 ++- .../scala/utils/SegControllerGenerator.scala | 30 +- 12 files changed, 425 insertions(+), 240 deletions(-) create mode 100644 .scalafmt.conf diff --git a/.scalafmt.conf b/.scalafmt.conf new file mode 100644 index 0000000..cbc03c3 --- /dev/null +++ b/.scalafmt.conf @@ -0,0 +1,2 @@ +version = 3.7.17 +runner.dialect = scala213source3 diff --git a/flake.nix b/flake.nix index 74de402..5c9c6f7 100644 --- a/flake.nix +++ b/flake.nix @@ -50,6 +50,13 @@ enable = true; types_or = pkgs.lib.mkForce [ "c" "c++" ]; }; + scalafmt = { + enable = true; + package = pkgs.scalafmt; + name = "Scalafmt"; + types = [ "scala" ]; + entry = "${pkgs.scalafmt}/bin/scalafmt --non-interactive"; + }; }; }; }; diff --git a/npc/core/build.sbt b/npc/core/build.sbt index 3d0f4f8..e5de39d 100644 --- a/npc/core/build.sbt +++ b/npc/core/build.sbt @@ -1,9 +1,8 @@ -ThisBuild / scalaVersion := "2.13.12" -ThisBuild / version := "0.1.0" - +ThisBuild / scalaVersion := "2.13.12" +ThisBuild / version := "0.1.0" val chiselVersion = "6.2.0" -val circeVersion = "0.14.1" +val circeVersion = "0.14.1" lazy val root = (project in file(".")) .settings( @@ -12,7 +11,7 @@ lazy val root = (project in file(".")) "org.chipsalliance" %% "chisel" % chiselVersion, "edu.berkeley.cs" %% "chiseltest" % "6.0.0" % "test", "com.chuusai" %% "shapeless" % "2.3.3", - "com.github.scopt" %% "scopt" % "4.1.0", + "com.github.scopt" %% "scopt" % "4.1.0" ) ++ Seq( "io.circe" %% "circe-core", "io.circe" %% "circe-generic", @@ -23,7 +22,9 @@ lazy val root = (project in file(".")) "-deprecation", "-feature", "-Xcheckinit", - "-Ymacro-annotations", + "-Ymacro-annotations" ), - addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full), - ) \ No newline at end of file + addCompilerPlugin( + "org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full + ) + ) diff --git a/npc/core/src/main/scala/components/Mem.scala b/npc/core/src/main/scala/components/Mem.scala index a9d3e22..52889cb 100644 --- a/npc/core/src/main/scala/components/Mem.scala +++ b/npc/core/src/main/scala/components/Mem.scala @@ -24,7 +24,8 @@ class RamControlInterface(addrWidth: Int) extends Bundle { /* FIXME: Extends here might not be the best solution. * We need a way to merge two bundles together */ -class RamInterface[T <: Data](tpe: T, addrWidth: Int) extends RamControlInterface(addrWidth) { +class RamInterface[T <: Data](tpe: T, addrWidth: Int) + extends RamControlInterface(addrWidth) { val clock = Input(Clock()) val reset = Input(Reset()) val writeAddr = Input(UInt(addrWidth.W)) diff --git a/npc/core/src/main/scala/components/ProgramCounter.scala b/npc/core/src/main/scala/components/ProgramCounter.scala index 01ac115..287ca7f 100644 --- a/npc/core/src/main/scala/components/ProgramCounter.scala +++ b/npc/core/src/main/scala/components/ProgramCounter.scala @@ -30,11 +30,11 @@ class ProgramCounter[T <: UInt](tpe: T) extends Module { // pc := in.pcSrcs(control.srcSelect.asUInt) import control.SrcSelect._ - when( control.useImmB === true.B ) { + when(control.useImmB === true.B) { pc_reg := pc_reg + in.immB - }. elsewhen( control.srcSelect === pStaticNpc) { + }.elsewhen(control.srcSelect === pStaticNpc) { pc_reg := pc_reg + 4.U - }. elsewhen( control.srcSelect === pExeOut) { + }.elsewhen(control.srcSelect === pExeOut) { pc_reg := in.exeOut } out := pc_reg diff --git a/npc/core/src/main/scala/components/RegisterFile.scala b/npc/core/src/main/scala/components/RegisterFile.scala index b5d1b63..fe646fd 100644 --- a/npc/core/src/main/scala/components/RegisterFile.scala +++ b/npc/core/src/main/scala/components/RegisterFile.scala @@ -5,7 +5,7 @@ import chisel3.util.log2Ceil import chisel3.util.UIntToOH import chisel3.util.MuxLookup import chisel3.experimental.Trace._ -import shapeless.{ HList, HNil, :: } +import shapeless.{HList, HNil, ::} class RegControl extends Bundle { object WriteSelect extends ChiselEnum { @@ -21,7 +21,8 @@ class RegControl extends Bundle { traceName(writeEnable) } -class RegisterFile[T <: Data](tpe: T, regCount: Int, numReadPorts: Int) extends Module { +class RegisterFile[T <: Data](tpe: T, regCount: Int, numReadPorts: Int) + extends Module { require(numReadPorts >= 0) val control = IO(new RegControl) val dataAddrWidth = log2Ceil(regCount).W @@ -40,7 +41,10 @@ class RegisterFile[T <: Data](tpe: T, regCount: Int, numReadPorts: Int) extends for ((reg, i) <- regFile.zipWithIndex.tail) { reg := Mux( - writeAddrOH(i.U(log2Ceil(regCount).W)) && control.writeEnable, in.writeData(control.writeSelect.asUInt), reg) + writeAddrOH(i.U(log2Ceil(regCount).W)) && control.writeEnable, + in.writeData(control.writeSelect.asUInt), + reg + ) } regFile(0) := 0.U diff --git a/npc/core/src/main/scala/top/ArgParse.scala b/npc/core/src/main/scala/top/ArgParse.scala index b430a70..1b8cf41 100644 --- a/npc/core/src/main/scala/top/ArgParse.scala +++ b/npc/core/src/main/scala/top/ArgParse.scala @@ -1,16 +1,16 @@ package flow -import scopt.{ OParser, DefaultOEffectSetup } +import scopt.{OParser, DefaultOEffectSetup} import java.io.File case class CliOptions( targetDir: File = new File("."), configFile: Option[File] = None, argsFile: Option[File] = None, - verilatorConfigFileOut: File = new File("conf.vlt"), + verilatorConfigFileOut: File = new File("conf.vlt") ) { val builder = OParser.builder[CliOptions] - val parser = { + val parser = { import builder._ OParser.sequence( programName("flow"), @@ -33,14 +33,19 @@ case class CliOptions( def parse(args: Array[String]): CliOptions = { OParser.runParser(parser, args, CliOptions()) match { case (result, effects) => - OParser.runEffects(effects, new DefaultOEffectSetup { - // ignore terminate - override def terminate(exitState: Either[String, Unit]): Unit = () - }) + OParser.runEffects( + effects, + new DefaultOEffectSetup { + // ignore terminate + override def terminate(exitState: Either[String, Unit]): Unit = () + } + ) result match { case Some(cliOptions: CliOptions) => { return cliOptions } - case _ => { throw new IllegalArgumentException("Wrong command line argument") } + case _ => { + throw new IllegalArgumentException("Wrong command line argument") + } } } } diff --git a/npc/core/src/main/scala/top/Config.scala b/npc/core/src/main/scala/top/Config.scala index aa58107..515c080 100644 --- a/npc/core/src/main/scala/top/Config.scala +++ b/npc/core/src/main/scala/top/Config.scala @@ -3,14 +3,14 @@ package flow import io.circe.generic.JsonCodec // Which group of signals to trace -@JsonCodec case class TraceConfig ( - enable: Boolean = false, - registers: Array[Int] = Array(), - mem: Array[(Int, Int)] = Array(), +@JsonCodec case class TraceConfig( + enable: Boolean = false, + registers: Array[Int] = Array(), + mem: Array[(Int, Int)] = Array() ) @JsonCodec case class Config( - // Whether to enable Difftest - enableDifftest: Boolean = true, - traceConfig: TraceConfig = TraceConfig(), + // Whether to enable Difftest + enableDifftest: Boolean = true, + traceConfig: TraceConfig = TraceConfig() ) diff --git a/npc/core/src/main/scala/top/FlowMain.scala b/npc/core/src/main/scala/top/FlowMain.scala index 3377689..edce4d4 100644 --- a/npc/core/src/main/scala/top/FlowMain.scala +++ b/npc/core/src/main/scala/top/FlowMain.scala @@ -8,7 +8,7 @@ import chisel3.experimental.Trace._ import shapeless.{HNil, ::} import shapeless.HList import shapeless.ops.coproduct.Prepend -import chisel3.util.{ BinaryMemoryFile, HexMemoryFile } +import chisel3.util.{BinaryMemoryFile, HexMemoryFile} import chisel3.experimental.Trace import scala.collection.IndexedSeqView @@ -18,6 +18,7 @@ import flow.components.RamControlInterface object RV32Inst { private val bp = BitPat + // format: off val lui = this.bp("b???????_?????_?????_???_?????_01101_11") val auipc = this.bp("b???????_?????_?????_???_?????_00101_11") @@ -72,28 +73,33 @@ object RV32Inst { val remu = this.bp("b0000001_?????_?????_111_?????_01100_11") val inv = this.bp("b???????_?????_?????_???_?????_?????_??") + // format: on } import flow.components.{RegControl, PcControlInterface, ALUControlInterface} class Control(width: Int) extends RawModule { // Helpers - class WrapList[T](vl: T) { type Type = T; val v = vl} + class WrapList[T](vl: T) { type Type = T; val v = vl } object wrap extends Poly1 { implicit def default[A] = at[A](Right(_).withLeft[Int]) } def lit(x: Element) = { x.litValue.toInt } def toBits(t: dst.Type): BitPat = { val list = t.toList - list.map(e => e match { - case Right(x) => BitPat(lit(x).U(x.getWidth.W)) - case Left(x) => BitPat.dontCare(x) - }).reduceLeft(_ ## _) + list + .map(e => + e match { + case Right(x) => BitPat(lit(x).U(x.getWidth.W)) + case Left(x) => BitPat.dontCare(x) + } + ) + .reduceLeft(_ ## _) } val r = Right def l[T <: Any](x: T) = x match { case x: ChiselEnum => Left(log2Ceil(x.all.length)) - case x: Data => Left(x.getWidth) - case _ => throw new IllegalArgumentException + case x: Data => Left(x.getWidth) + case _ => throw new IllegalArgumentException } val inst = IO(Input(UInt(width.W))) @@ -103,11 +109,12 @@ class Control(width: Int) extends RawModule { val alu = IO(Flipped(new ALUControlInterface)) val ram = IO(Flipped(new RamControlInterface(32))) - val dst = new WrapList(( - reg.ctrlBindPorts ++ - pc.ctrlBindPorts ++ - alu.ctrlBindPorts ++ - ram.ctrlBindPorts).map(wrap)) + val dst = new WrapList( + (reg.ctrlBindPorts ++ + pc.ctrlBindPorts ++ + alu.ctrlBindPorts ++ + ram.ctrlBindPorts).map(wrap) + ) val dstList = dst.v.toList val controlWidth = dstList.map(_.toOption.get.getWidth).reduce(_ + _) @@ -124,209 +131,286 @@ class Control(width: Int) extends RawModule { import alu.SrcBSelect._ import pc._ import RV32Inst._ + // format: off val ControlMapping: Array[(BitPat, dst.Type)] = Array( // Regs | writeEnable :: writeSelect :: HNil // PC | useImmB :: srcSelect :: HNil // Exe | op :: srcASelect :: srcBSelect :: signExt :: HNil // Mem | valid :: writeMask :: writeEnable :: HNil - (lui , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc):: - r(aOpAdd) :: r(aSrcAZero) :: r(aSrcBImmU) :: r(false.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (lui , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc):: + r(aOpAdd) :: r(aSrcAZero) :: r(aSrcBImmU) :: r(false.B) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (auipc , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc):: - r(aOpAdd) :: r(aSrcAPc) :: r(aSrcBImmU) :: r(false.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (auipc , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc):: + r(aOpAdd) :: r(aSrcAPc) :: r(aSrcBImmU) :: r(false.B) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), // ---- Control Transfer Instructions ---- - (jal , (r(true.B) :: r(rNpc) :: - r(false.B) :: r(pExeOut) :: - r(aOpAdd) :: r(aSrcAPc) :: r(aSrcBImmJ) :: r(false.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (jal , ( + r(true.B) :: r(rNpc) :: + r(false.B) :: r(pExeOut) :: + r(aOpAdd) :: r(aSrcAPc) :: r(aSrcBImmJ) :: r(false.B) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (jalr , (r(true.B) :: r(rNpc) :: - r(false.B) :: r(pExeOut) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (jalr , ( + r(true.B) :: r(rNpc) :: + r(false.B) :: r(pExeOut) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (beq , (r(false.B) :: l(WriteSelect) :: - r(true.B) :: r(pStaticNpc) :: - r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (beq , ( + r(false.B) :: l(WriteSelect) :: + r(true.B) :: r(pStaticNpc) :: + r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (bne , (r(false.B) :: l(WriteSelect) :: - r(true.B) :: r(pStaticNpc) :: - r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (bne , ( + r(false.B) :: l(WriteSelect) :: + r(true.B) :: r(pStaticNpc) :: + r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (blt , (r(false.B) :: l(WriteSelect) :: - r(true.B) :: r(pStaticNpc) :: - r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(true.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (blt , ( + r(false.B) :: l(WriteSelect) :: + r(true.B) :: r(pStaticNpc) :: + r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(true.B) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (bge , (r(false.B) :: l(WriteSelect) :: - r(true.B) :: r(pStaticNpc) :: - r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(true.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (bge , ( + r(false.B) :: l(WriteSelect) :: + r(true.B) :: r(pStaticNpc) :: + r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(true.B) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (bltu , (r(false.B) :: l(WriteSelect):: - r(true.B) :: r(pStaticNpc) :: - r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(false.B) :: - r(false.B) :: l(UInt(4.W)) :: r(false.B) :: HNil)), + (bltu , ( + r(false.B) :: l(WriteSelect):: + r(true.B) :: r(pStaticNpc) :: + r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(false.B) :: + r(false.B) :: l(UInt(4.W)) :: r(false.B) :: HNil + )), - (bgeu , (r(false.B) :: l(WriteSelect):: - r(true.B) :: r(pStaticNpc) :: - r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(false.B) :: - r(false.B) :: l(UInt(4.W)) :: r(false.B) :: HNil)), + (bgeu , ( + r(false.B) :: l(WriteSelect):: + r(true.B) :: r(pStaticNpc) :: + r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(false.B) :: + r(false.B) :: l(UInt(4.W)) :: r(false.B) :: HNil + )), // ---- Memory Access Instructions ---- - (lb , (r(true.B) :: r(rMemOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(true.B) :: r(1.U(4.W)) :: r(false.B) :: HNil)), + (lb , ( + r(true.B) :: r(rMemOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(true.B) :: r(1.U(4.W)) :: r(false.B) :: HNil + )), - (lbu , (r(true.B) :: r(rMemOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(true.B) :: r(0.U(4.W)) :: r(false.B) :: HNil)), + (lbu , ( + r(true.B) :: r(rMemOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(true.B) :: r(0.U(4.W)) :: r(false.B) :: HNil + )), - (lh , (r(true.B) :: r(rMemOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(true.B) :: r(3.U(4.W)) :: r(false.B) :: HNil)), + (lh , ( + r(true.B) :: r(rMemOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(true.B) :: r(3.U(4.W)) :: r(false.B) :: HNil + )), - (lhu , (r(true.B) :: r(rMemOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(true.B) :: r(2.U(4.W)) :: r(false.B) :: HNil)), + (lhu , ( + r(true.B) :: r(rMemOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(true.B) :: r(2.U(4.W)) :: r(false.B) :: HNil + )), - (lw , (r(true.B) :: r(rMemOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(true.B) :: r(14.U(4.W)) :: r(false.B) :: HNil)), + (lw , ( + r(true.B) :: r(rMemOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(true.B) :: r(14.U(4.W)) :: r(false.B) :: HNil + )), - (sb , (r(false.B) :: l(WriteSelect):: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmS) :: l(Bool()) :: - r(true.B) :: r(1.U(4.W)) :: r(true.B) :: HNil)), + (sb , ( + r(false.B) :: l(WriteSelect):: + r(false.B) :: r(pStaticNpc) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmS) :: l(Bool()) :: + r(true.B) :: r(1.U(4.W)) :: r(true.B) :: HNil + )), - (sh , (r(false.B) :: l(WriteSelect):: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmS) :: l(Bool()) :: - r(true.B) :: r(3.U(4.W)) :: r(true.B) :: HNil)), + (sh , ( + r(false.B) :: l(WriteSelect):: + r(false.B) :: r(pStaticNpc) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmS) :: l(Bool()) :: + r(true.B) :: r(3.U(4.W)) :: r(true.B) :: HNil + )), - (sw , (r(false.B) :: l(WriteSelect):: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmS) :: l(Bool()) :: - r(true.B) :: r(15.U(4.W)) :: r(true.B) :: HNil)), + (sw , ( + r(false.B) :: l(WriteSelect):: + r(false.B) :: r(pStaticNpc) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmS) :: l(Bool()) :: + r(true.B) :: r(15.U(4.W)) :: r(true.B) :: HNil + )), // ---- Integer Computational Instructions --- - (addi , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (addi , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (slti , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBImmI) :: r(true.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (slti , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBImmI) :: r(true.B) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (sltiu , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (sltiu , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (xori , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpXor) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (xori , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpXor) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (ori , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpOr) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (ori , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpOr) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (andi , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpAnd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (andi , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpAnd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (slli , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpSll) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (slli , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpSll) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (srli , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpSrl) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (srli , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpSrl) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (srai , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpSra) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (srai , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpSra) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (add , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (add , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (sub , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpSub) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (sub , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpSub) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (sll , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpSll) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (sll , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpSll) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (slt , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(true.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (slt , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpSlt) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(true.B) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (sltu , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(false.B) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (sltu , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpSltu) :: r(aSrcARs1) :: r(aSrcBRs2) :: r(false.B) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (xor , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpXor) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (xor , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpXor) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (srl , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpSrl) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (srl , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpSrl) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (sra , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpSra) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (sra , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpSra) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (or , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpOr) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (or , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpOr) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), - (and , (r(true.B) :: r(rAluOut) :: - r(false.B) :: r(pStaticNpc) :: - r(aOpAnd) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: - r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), + (and , ( + r(true.B) :: r(rAluOut) :: + r(false.B) :: r(pStaticNpc) :: + r(aOpAnd) :: r(aSrcARs1) :: r(aSrcBRs2) :: l(Bool()) :: + r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil + )), ) + // format: on val default = BitPat(0.U(controlWidth.W)) // println(s"ControlMapping = ${ControlMapping.map(it => (it._1 -> toBits(it._2))).foreach(x => println(x._2))}\n") val out = decoder( inst, - TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default)) + TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default) + ) val srcList = slices.map(s => out(s._1, s._2)) assert(out != default) @@ -363,7 +447,13 @@ class Flow extends Module { val npc = Wire(dataType) npc := pc.out + 4.U pc.in.exeOut := alu.out.result - pc.in.immB := Cat(Fill(20, inst(31)), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)) + pc.in.immB := Cat( + Fill(20, inst(31)), + inst(7), + inst(30, 25), + inst(11, 8), + 0.U(1.W) + ) control.inst := inst reg.control <> control.reg @@ -387,7 +477,8 @@ class Flow extends Module { Fill(8, ram.io.writeMask(3)), Fill(8, ram.io.writeMask(2)), Fill(8, ram.io.writeMask(1)), - "b11111111".U) + "b11111111".U + ) val doSignExt = control.ram.writeMask(0) val signExt16 = control.ram.writeMask(1) @@ -395,10 +486,14 @@ class Flow extends Module { reg.in.writeData(lit(rMemOut)) := maskedData // printf(cf"!doSignExt\n") }.elsewhen(signExt16) { - reg.in.writeData(lit(rMemOut)) := Cat(Fill(16, maskedData(15)), maskedData(15, 0)) + reg.in.writeData(lit(rMemOut)) := Cat( + Fill(16, maskedData(15)), + maskedData(15, 0) + ) // printf(cf"elsewhen\n") }.otherwise { - reg.in.writeData(lit(rMemOut)) := Cat(Fill(24, maskedData(7)), maskedData(7, 0)) + reg.in + .writeData(lit(rMemOut)) := Cat(Fill(24, maskedData(7)), maskedData(7, 0)) // printf(cf"otherwise\n") } // printf(cf"maskedData = ${maskedData}, writeData = ${reg.in.writeData(lit(rMemOut))}\n") @@ -427,8 +522,21 @@ class Flow extends Module { alu.in.b(lit(aSrcBRs2)) := reg.out.src(1) // alu.in.b(lit(aSrcBImmI)) := inst(31, 20).pad(aSrcBImmI.getWidth) alu.in.b(lit(aSrcBImmI)) := Cat(Fill(20, inst(31)), inst(31, 20)) - alu.in.b(lit(aSrcBImmJ)) := Cat(Fill(12, inst(31)), inst(19, 12), inst(20), inst(30, 25), inst(24, 21), 0.U(1.W)) - alu.in.b(lit(aSrcBImmS)) := Cat(Fill(20, inst(31)), inst(31), inst(30, 25), inst(11, 8), inst(7)) + alu.in.b(lit(aSrcBImmJ)) := Cat( + Fill(12, inst(31)), + inst(19, 12), + inst(20), + inst(30, 25), + inst(24, 21), + 0.U(1.W) + ) + alu.in.b(lit(aSrcBImmS)) := Cat( + Fill(20, inst(31)), + inst(31), + inst(30, 25), + inst(11, 8), + inst(7) + ) alu.in.b(lit(aSrcBImmU)) := Cat(inst(31, 12), 0.U(12.W)) Trace.traceName(pc.out) diff --git a/npc/core/src/main/scala/top/Main.scala b/npc/core/src/main/scala/top/Main.scala index 6de6893..ba4ce99 100644 --- a/npc/core/src/main/scala/top/Main.scala +++ b/npc/core/src/main/scala/top/Main.scala @@ -13,7 +13,6 @@ import java.io.PrintWriter import scala.io.Source import java.io.File - // TODO: Generate verilator config file object VerilogMain extends App { @@ -27,46 +26,58 @@ object VerilogMain extends App { source.close() io.circe.parser.decode[Config](jsonString) match { case Right(x) => x - case Left(e) => throw e + case Left(e) => throw e } } case None => Config(traceConfig = TraceConfig(enable = true)) } val annos = (new ChiselStage).execute( - Array("--target-dir", opt.targetDir.toString, "--target", "systemverilog", "--split-verilog", "--full-stacktrace"), + Array( + "--target-dir", + opt.targetDir.toString, + "--target", + "systemverilog", + "--split-verilog", + "--full-stacktrace" + ), Seq( - - ) ++ (if(config.traceConfig.enable) Seq(ChiselGeneratorAnnotation(() => new Flow)) else Seq()) + ) ++ (if (config.traceConfig.enable) + Seq(ChiselGeneratorAnnotation(() => new Flow)) + else Seq()) ) - if(config.traceConfig.enable) { - val dut = annos.collectFirst { case DesignAnnotation(dut) => dut }.get.asInstanceOf[Flow] + if (config.traceConfig.enable) { + val dut = annos + .collectFirst { case DesignAnnotation(dut) => dut } + .get + .asInstanceOf[Flow] - val verilatorConfigSeq = finalTargetMap(annos) - .values - .flatten + val verilatorConfigSeq = finalTargetMap(annos).values.flatten .map(ct => - s"""public_flat_rd -module "${ - ct.tokens.collectFirst { case OfModule(m) => m }.get - }" -var "${ct.tokens.collectFirst { case Ref(r) => r }.get}"""") - finalTargetMap(annos) - .values - .flatten - .foreach( - ct => println(s"""TOP.${ct.circuit}.${ct.path.map { case (Instance(i), _) => i }.mkString(".")}.${ct.tokens.collectFirst { - case Ref(r) => r - }.get}""") + s"""public_flat_rd -module "${ct.tokens.collectFirst { + case OfModule(m) => m + }.get}" -var "${ct.tokens.collectFirst { case Ref(r) => r }.get}"""" + ) + finalTargetMap(annos).values.flatten + .foreach(ct => + println(s"""TOP.${ct.circuit}.${ct.path + .map { case (Instance(i), _) => i } + .mkString(".")}.${ct.tokens.collectFirst { case Ref(r) => + r + }.get}""") ) - val verilatorConfigWriter = new PrintWriter(new File(opt.targetDir, opt.verilatorConfigFileOut.toString())) + val verilatorConfigWriter = new PrintWriter( + new File(opt.targetDir, opt.verilatorConfigFileOut.toString()) + ) verilatorConfigWriter.write("`verilator_config\n") try { - for(ct <- verilatorConfigSeq) { + for (ct <- verilatorConfigSeq) { verilatorConfigWriter.println(ct) } } finally { verilatorConfigWriter.close() } } -} \ No newline at end of file +} diff --git a/npc/core/src/main/scala/utils/Keyboard.scala b/npc/core/src/main/scala/utils/Keyboard.scala index 716c304..fd37a9c 100644 --- a/npc/core/src/main/scala/utils/Keyboard.scala +++ b/npc/core/src/main/scala/utils/Keyboard.scala @@ -55,7 +55,7 @@ class KeyboardController extends Module { } class KeyboardSegController extends Module { - val io = IO(new Bundle{ + val io = IO(new Bundle { val keycode = Flipped(Decoupled(UInt(8.W))) val segs = Vec(8, UInt(8.W)) }) @@ -66,30 +66,60 @@ class KeyboardSegController extends Module { // 0x1C.U -> 0x41.U, ... val keycode_to_ascii = Seq( - 0x1C.U, 0x32.U, 0x21.U, 0x23.U, 0x24.U, 0x2B.U, - 0x34.U, 0x33.U, 0x43.U, 0x3B.U, 0x42.U, 0x4B.U, - 0x3A.U, 0x31.U, 0x44.U, 0x4D.U, 0x15.U, 0x2D.U, - 0x1B.U, 0x2C.U, 0x3C.U, 0x2A.U, 0x1D.U, 0x22.U, - 0x35.U, 0x1A.U, 0x45.U, 0x16.U, 0x1E.U, 0x26.U, - 0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U, - ).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U)) + 0x1c.U, + 0x32.U, + 0x21.U, + 0x23.U, + 0x24.U, + 0x2b.U, + 0x34.U, + 0x33.U, + 0x43.U, + 0x3b.U, + 0x42.U, + 0x4b.U, + 0x3a.U, + 0x31.U, + 0x44.U, + 0x4d.U, + 0x15.U, + 0x2d.U, + 0x1b.U, + 0x2c.U, + 0x3c.U, + 0x2a.U, + 0x1d.U, + 0x22.U, + 0x35.U, + 0x1a.U, + 0x45.U, + 0x16.U, + 0x1e.U, + 0x26.U, + 0x25.U, + 0x2e.U, + 0x36.U, + 0x3d.U, + 0x3e.U, + 0x46.U + ).zip(((0x41 to 0x5a) ++ (0x30 to 0x39)).map(_.U)) val keycode = RegInit(0.U(8.W)) - val counter = Counter(0xFF) + val counter = Counter(0xff) val release_state = RegInit(Bool(), false.B) when(io.keycode.ready && io.keycode.valid) { - when(io.keycode.bits === 0xF0.U) { + when(io.keycode.bits === 0xf0.U) { release_state := true.B }.elsewhen(!release_state) { counter.inc() keycode := io.keycode.bits - }.otherwise{ + }.otherwise { // Release code on io.keycode.bits release_state := false.B } } - val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4)) + val keycode_digits = VecInit(keycode(3, 0)) ++ VecInit(keycode(7, 4)) val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii) val seg_contoller = Module(new SegControllerGenerator(8, UInt(8.W))) diff --git a/npc/core/src/main/scala/utils/SegControllerGenerator.scala b/npc/core/src/main/scala/utils/SegControllerGenerator.scala index 7f2cb68..fdfcbc8 100644 --- a/npc/core/src/main/scala/utils/SegControllerGenerator.scala +++ b/npc/core/src/main/scala/utils/SegControllerGenerator.scala @@ -9,16 +9,32 @@ class SegControllerGenerator[T <: Data](seg_count: Int, t: T) extends Module { val in_segs = Input(Vec(seg_count / ((t.getWidth + 3) / 4), t)) val segs = Output(Vec(seg_count, UInt(8.W))) }) - val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq( - "b00000011".U, "b10011111".U, "b00100101".U, "b00001101".U, - "b10011001".U, "b01001001".U, "b01000001".U, "b00011111".U, - "b00000001".U, "b00001001".U, "b00010001".U, "b11000001".U, - "b01100011".U, "b10000101".U, "b01100001".U, "b01110001".U, - )) + val digit_to_seg = ((0 until 16) + .map(_.U)) + .zip( + Seq( + "b00000011".U, + "b10011111".U, + "b00100101".U, + "b00001101".U, + "b10011001".U, + "b01001001".U, + "b01000001".U, + "b00011111".U, + "b00000001".U, + "b00001001".U, + "b00010001".U, + "b11000001".U, + "b01100011".U, + "b10000101".U, + "b01100001".U, + "b01110001".U + ) + ) val vec = io.in_segs.asTypeOf(Vec(seg_count, UInt(4.W))) val segs = VecInit(Seq.fill(seg_count)(0.U(8.W))) - segs := vec.map(MuxLookup(_, 0xFF.U)(digit_to_seg)) + segs := vec.map(MuxLookup(_, 0xff.U)(digit_to_seg)) io.segs := segs }