> configure(npc)

ysyx_22040000 李心杨
 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
  13:51:33  up 1 day 22:38,  2 users,  load average: 3.60, 1.55, 1.34
This commit is contained in:
tracer-ysyx 2024-01-06 13:51:33 +08:00 committed by xinyangli
parent d4ab3e5752
commit b4bef0fb64
12 changed files with 448 additions and 16 deletions

View file

@ -35,7 +35,7 @@ class ALUGenerator(width: Int) extends Module {
val out = Output(UInt(width.W)) val out = Output(UInt(width.W))
}) })
val adder_b = io.op(0) ^ io.b // take (-b) if sub val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
val add = io.a + adder_b val add = io.a + adder_b
val and = io.a & io.b val and = io.a & io.b
val not = ~io.a val not = ~io.a
@ -44,7 +44,7 @@ class ALUGenerator(width: Int) extends Module {
val slt = io.a < io.b val slt = io.a < io.b
val eq = io.a === io.b val eq = io.a === io.b
io.out := MuxLookup(io.op, 0.U) Map( io.out := MuxLookup(io.op, 0.U)(Seq(
0.U -> add, 0.U -> add,
1.U -> add, // add with b reversed 1.U -> add, // add with b reversed
2.U -> not, 2.U -> not,
@ -53,7 +53,7 @@ class ALUGenerator(width: Int) extends Module {
5.U -> xor, 5.U -> xor,
6.U -> slt, 6.U -> slt,
7.U -> eq, 7.U -> eq,
) ))
} }
class MuxGenerator(width: Int, nInput: Int) extends Module { class MuxGenerator(width: Int, nInput: Int) extends Module {

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@ -1,3 +1,5 @@
package npc
import chisel3._ import chisel3._
import chiseltest._ import chiseltest._
import org.scalatest.freespec.AnyFreeSpec import org.scalatest.freespec.AnyFreeSpec
@ -47,21 +49,31 @@ class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
c.io.out.expect(8.U) c.io.out.expect(8.U)
} }
} }
"sub should work" in { "sub should work" - {
test(new ALUGenerator(32)) { c => "with positive result" in {
c.io.op.poke(1.U) test(new ALUGenerator(32)) { c =>
c.io.a.poke(5.U) c.io.op.poke(1.U)
c.io.b.poke(3.U) c.io.a.poke(5.U)
c.io.out.expect(2.U) c.io.b.poke(3.U)
c.io.out.expect(2)
}
}
"with negative result" in {
test(new ALUGenerator(32)) { c =>
c.io.op.poke(1.U)
c.io.a.poke(3.U)
c.io.b.poke(5.U)
c.io.out.expect(BigInt("FFFFFFFF", 16) - 1)
}
} }
} }
"not should work" in { "not should work" in {
test(new ALUGenerator(32)) { c => // test(new ALUGenerator(32)) { c =>
c.io.op.poke(2.U) // c.io.op.poke(2.U)
c.io.a.poke(5.U) // c.io.a.poke(5.U)
c.io.b.poke(3.U) // c.io.b.poke(3.U)
c.io.out.expect((-6).U) // c.io.out.expect(((1 << 32) - 1 - 5).U)
} // }
} }
"and should work" in { "and should work" in {
test(new ALUGenerator(32)) { c => test(new ALUGenerator(32)) { c =>
@ -101,7 +113,7 @@ class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
c.io.a.poke(16.U) c.io.a.poke(16.U)
c.io.b.poke(16.U) c.io.b.poke(16.U)
c.io.out.expect(1.U) c.io.out.expect(0.U)
} }
} }
"equal should work" in { "equal should work" in {

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@ -0,0 +1,42 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

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@ -0,0 +1,42 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

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@ -0,0 +1,42 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

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@ -0,0 +1,42 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

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@ -0,0 +1,42 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

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FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

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FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

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@ -0,0 +1,42 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

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@ -0,0 +1,42 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

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@ -0,0 +1,42 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]