xin/ysyx-workbench
1
0
Fork 0
Code Issues Pull requests 1 Projects Releases Packages Wiki Activity Actions

> build_npc_VKeyboard_nvboard

Browse source 
ysyx_22040000 李心杨
 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
  21:40:52  up 2 days 20:41,  2 users,  load average: 2.26, 1.40, 1.22
This commit is contained in:
tracer-ysyx 2024-01-10 21:40:52 +08:00 committed by xinyangli
parent cbff32c35c
commit afb0748963
2 changed files with 7 additions and 14 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
npc/core/src/main/scala/Keyboard.scala
View file

@ -91,7 +91,7 @@ class KeyboardSegController extends Module {
val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4)) val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii) val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
val seg_contoller = SegControllerGenerator(8) val seg_contoller = Module(new SegControllerGenerator(8, UInt(8.W)))
seg_contoller.io.in_segs := VecInit(Seq(keycode, ascii, counter.value, 0.U)) seg_contoller.io.in_segs := VecInit(Seq(keycode, ascii, counter.value, 0.U))
io.segs := seg_contoller.io.segs io.segs := seg_contoller.io.segs

19
npc/core/src/main/scala/SegControllerGenerator.scala
View file

@ -4,9 +4,9 @@ import chisel3._
import chisel3.util._ import chisel3.util._
import chisel3.util.log2Ceil import chisel3.util.log2Ceil
class SegControllerGenerator(seg_count: Int) extends Module { class SegControllerGenerator[T <: Data](seg_count: Int, t: T) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val in_segs = Input(Vec(seg_count, UInt())) val in_segs = Input(Vec(seg_count / ((t.getWidth + 3) / 4), t))
val segs = Output(Vec(seg_count, UInt(8.W))) val segs = Output(Vec(seg_count, UInt(8.W)))
}) })
val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq( val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq(
@ -15,17 +15,10 @@ class SegControllerGenerator(seg_count: Int) extends Module {
"b00000001".U, "b00001001".U, "b00010001".U, "b11000001".U, "b00000001".U, "b00001001".U, "b00010001".U, "b11000001".U,
"b01100011".U, "b10000101".U, "b01100001".U, "b01110001".U, "b01100011".U, "b10000101".U, "b01100001".U, "b01110001".U,
)) ))
val vec_size = (io.in_segs.getWidth + 3) / 4 val vec = io.in_segs.asTypeOf(Vec(seg_count, UInt(4.W)))
val vec = io.in_segs.asTypeOf(Vec(vec_size, UInt(4.W)))
val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(8.W)))) val segs = VecInit(Seq.fill(seg_count)(0.U(8.W)))
seg_regs := vec.map(MuxLookup(_, 0xFF.U)(digit_to_seg)) ++ Seq(0xFF.U, 0xFF.U) segs := vec.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
io.segs := seg_regs io.segs := segs
}
object SegControllerGenerator {
def apply(seg_count: Int): SegControllerGenerator = {
new SegControllerGenerator(seg_count)
}
} }