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> configure(npc)

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ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  00:33:44  up 3 days 15:24,  2 users,  load average: 1.20, 0.75, 0.43
This commit is contained in:
tracer-ysyx 2024-03-13 00:33:44 +08:00 committed by xinyangli
parent 0cfa9d2eef
commit aeed35376f
2 changed files with 18 additions and 26 deletions
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42
npc/core/src/main/scala/Main.scala
View file

@ -63,47 +63,39 @@ class Control(width: Int) extends Module {
alu.op := alu.OpSelect(0.U)
pc.srcSelect := pc.SrcSelect(0.U)
// val out = decoder(
// inst,
// TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default))
val table = TruthTable(
(0 until 16).map { i =>
BitPat(i.U(4.W)) -> BitPat((1 << i).U(16.W))
},
BitPat.dontCare(16)
)
val out = decoder(
inst,
TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default))
val out = decoder.qmc(inst(3,0), table)
val dstList = dst.toList
val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
val slices = reversePrefixSum.zip(reversePrefixSum.tail)
val srcList = slices.map(s => out(s._1 - 1, s._2))
// val dstList = dst.toList
// val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
// val slices = reversePrefixSum.zip(reversePrefixSum.tail)
// val srcList = slices.map(s => out(s._1 - 1, s._2))
// srcList
// .zip(dstList)
// .foreach({ case (src, dst) =>
// dst := src.asTypeOf(dst)
// })
srcList
.zip(dstList)
.foreach({ case (src, dst) =>
dst := src.asTypeOf(dst)
})
}
import flow.components.{RegisterFile, RegFileInterface, ProgramCounter, ALU}
import chisel3.util.experimental.loadMemoryFromFileInline
class Flow extends Module {
// val dataType = UInt(32.W)
val dataType = UInt(32.W)
val ram = SRAM(
size = 128 * 1024 * 1024,
tpe = UInt(32.W),
tpe = dataType,
numReadPorts = 2,
numWritePorts = 1,
numReadwritePorts = 0,
// memoryFile = HexMemoryFile(memoryFile)
)
val control = Module(new Control(32))
val reg = RegisterFile(32, UInt(32.W), 2, 2)
val pc = Module(new ProgramCounter(UInt(32.W)))
val alu = Module(new ALU(UInt(32.W)))
val reg = RegisterFile(32, dataType, 2, 2)
val pc = Module(new ProgramCounter(dataType))
val alu = Module(new ALU(dataType))
ram.readPorts(0).enable := true.B
ram.readPorts(0).address := pc.out - 0x80000000L.U

2
npc/core/src/test/scala/Main.scala
View file

@ -39,7 +39,7 @@ class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
}
}
"should compile" in {
test(new Flow("../resource/addi.txt")).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
test(new Flow).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
c.clock.step(1)
}
}