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> configure(npc)

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ysyx_22040000 李心杨
 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
  14:44:17  up 2 days 13:45,  2 users,  load average: 1.18, 1.21, 1.18
This commit is contained in:
tracer-ysyx 2024-01-10 14:44:17 +08:00 committed by xinyangli
parent 0458aba520
commit abb76552fb
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4 changed files with 70 additions and 52 deletions
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14
npc/constr/Keyboard.nxdc
View file

@ -1,7 +1,11 @@
top=Keyboard
io_ps2_clk PS2_CLK
io_ps2_data PS2_DAT
io_segs_0 (SEG1A, SEG1B, SEG1C, SEG1D, SEG1E, SEG1F, SEG1G, DEC1P, SEG0A, SEG0B, SEG0C, SEG0D, SEG0E, SEG0F, SEG0G, DEC0P)
io_segs_1 (SEG3A, SEG3B, SEG3C, SEG3D, SEG3E, SEG3F, SEG3G, DEC3P, SEG2A, SEG2B, SEG2C, SEG2D, SEG2E, SEG2F, SEG2G, DEC2P)
io_segs_2 (SEG5A, SEG5B, SEG5C, SEG5D, SEG5E, SEG5F, SEG5G, DEC5P, SEG4A, SEG4B, SEG4C, SEG4D, SEG4E, SEG4F, SEG4G, DEC4P)
io_keycode_bits (SW7, SW6, SW5, SW4, SW3, SW2, SW1, SW0)
io_segs_0 (SEG0A, SEG0B, SEG0C, SEG0D, SEG0E, SEG0F, SEG0G, DEC0P)
io_segs_1 (SEG1A, SEG1B, SEG1C, SEG1D, SEG1E, SEG1F, SEG1G, DEC1P)
io_segs_2 (SEG2A, SEG2B, SEG2C, SEG2D, SEG2E, SEG2F, SEG2G, DEC2P)
io_segs_3 (SEG3A, SEG3B, SEG3C, SEG3D, SEG3E, SEG3F, SEG3G, DEC3P)
io_segs_4 (SEG4A, SEG4B, SEG4C, SEG4D, SEG4E, SEG4F, SEG4G, DEC4P)
io_segs_5 (SEG5A, SEG5B, SEG5C, SEG5D, SEG5E, SEG5F, SEG5G, DEC5P)
io_segs_6 (SEG6A, SEG6B, SEG6C, SEG6D, SEG6E, SEG6F, SEG6G, DEC6P)
io_segs_7 (SEG7A, SEG7B, SEG7C, SEG7D, SEG7E, SEG7F, SEG7G, DEC7P)

96
npc/core/src/main/scala/Keyboard.scala
View file

@ -4,6 +4,7 @@ import chisel3._
import chisel3.util.{Counter, Decoupled, Queue, Reverse, MuxLookup}
import npc.seg._
import upickle.implicits.key
class PS2Port extends Bundle {
val clk = Input(Bool())
@ -26,12 +27,12 @@ class KeyboardController extends Module {
val cycle_counter = Counter(11)
val concated_data = RegInit(0.U(8.W))
val queue_io = Wire(Flipped(Decoupled(UInt(8.W))))
val queue = Queue(queue_io, entries = 8)
val queue_in = Wire(Flipped(Decoupled(UInt(8.W))))
val queue = Queue(queue_in, entries = 8)
val received = RegInit(Bool(), false.B)
val pushed = RegNext(queue_io.valid && queue_io.ready, false.B)
queue_io.valid := false.B
queue_io.bits := Reverse(concated_data)
val pushed = RegNext(queue_in.valid && queue_in.ready, false.B)
queue_in.valid := false.B
queue_in.bits := Reverse(concated_data)
io.out <> queue
when(cycle_counter.value === 0.U) {
@ -49,9 +50,9 @@ class KeyboardController extends Module {
}
when(!pushed && received) {
queue_io.valid := true.B
queue_in.valid := true.B
}.elsewhen(pushed && received) {
queue_io.valid := false.B
queue_in.valid := false.B
received := false.B
}
}
@ -59,52 +60,55 @@ class KeyboardController extends Module {
class SegHandler(seg_count: Int) extends Module {
val io = IO(new Bundle {
val keycode = Flipped(Decoupled(UInt(8.W)))
val segs = Output(Vec(seg_count / 2, UInt(16.W)))
val segs = Output(Vec(seg_count, UInt(8.W)))
})
io.keycode.ready := DontCare
val seg_regs = RegInit(VecInit(Seq.fill(seg_count / 2)(0.U(16.W))))
val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(8.W))))
val last_keycode = RegInit(0.U(8.W))
val counter = Counter(0xFF)
val digit_to_seg = Seq(
0.U -> "b0111111".U, // 0
1.U ->"b0000110".U, // 1
2.U -> "b1011011".U, // 2
3.U -> "b1001111".U, // 3
4.U -> "b1100110".U, // 4
5.U -> "b1101101".U, // 5
6.U -> "b1111101".U, // 6
7.U -> "b0000111".U, // 7
8.U -> "b1111111".U, // 8
9.U -> "b1101111".U, // 9
10.U -> "b1110111".U, // A
11.U -> "b1111100".U, // B
12.U -> "b0111001".U, // C
13.U -> "b1011110".U, // D
14.U -> "b1111001".U, // E
15.U -> "b1110001".U // F
)
val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq(
"b11111101".U, // 0
"b01100000".U, // 1
"b11011010".U, // 2
"b11110010".U, // 3
"b01100110".U, // 4
"b10110110".U, // 5
"b10111110".U, // 6
"b11100000".U, // 7
"b11111110".U, // 8
"b11110110".U, // 9
"b11101110".U, // A
"b00111110".U, // B
"b10011100".U, // C
"b01111010".U, // D
"b10011110".U, // E
"b10001110".U // F
))
val keycode_digits = VecInit(io.keycode.bits(3,0)) ++ VecInit(io.keycode.bits(7,4))
val keycode_seg = keycode_digits.map(MuxLookup(_, 0.U)(digit_to_seg))
seg_regs := keycode_seg ++ keycode_seg ++ keycode_seg
io.segs := seg_regs
when(io.keycode.valid) {
val data = io.keycode.bits
val state_f0_received = RegNext(data === 0xF0.U, false.B)
io.keycode.ready := true.B
// Handle keycode based on current state
// (keyboard press counter) :: (ASCII code) :: (Keycode)
when(state_f0_received) {
// Release code
}.otherwise{
counter.inc()
last_keycode := io.keycode.bits
}
}.otherwise {
io.keycode.ready := false.B
}
// when(io.keycode.valid) {
// val data = io.keycode.bits
// val state_f0_received = RegNext(data === 0xF0.U, false.B)
// io.keycode.ready := true.B
// // Handle keycode based on current state
// // (keyboard press counter) :: (ASCII code) :: (Keycode)
// when(state_f0_received) {
// // Release code
// }.otherwise{
// counter.inc()
// last_keycode := io.keycode.bits
// }
// }.otherwise {
// io.keycode.ready := false.B
// }
seg_regs := Seq(counter.value, last_keycode, last_keycode).map(d => {
MuxLookup(d & 0xF.U, 0.U)(digit_to_seg) | (MuxLookup((d >> 4.U) & 0xF.U, 0.U)(digit_to_seg) << 8.U)
})
}

10
npc/core/src/test/scala/Keyboard.scala
View file

@ -63,3 +63,13 @@ class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
}
}
}
class SegSpec extends AnyFreeSpec with ChiselScalatestTester {
"try out vec" in {
test(new SegHandler(6)) {c =>
c.io.keycode.bits.poke(0xAC)
c.clock.step(1)
println(s"out: ${c.io.segs(0).peek().litValue}")
}
}
}

2
npc/csrc_nvboard/main.cpp
View file

@ -18,7 +18,7 @@ int main(int argc, char **argv, char **env) {
while (true) {
nvboard_update();
top->eval();
printf("%d, %d, %d", top->io_segs_0, top->io_segs_1, top->io_segs_2);
// printf("%d, %d, %d", top->io_segs_0, top->io_segs_1, top->io_segs_2);
}
delete top;
}