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> build_npc_VSegHandler_nvboard

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ysyx_22040000 李心杨
 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
  15:20:50  up 2 days 14:21,  2 users,  load average: 0.89, 1.09, 1.23
This commit is contained in:
tracer-ysyx 2024-01-10 15:20:50 +08:00 committed by xinyangli
parent df20ddd658
commit aaf894d5e6
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1 changed files with 36 additions and 21 deletions
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41
npc/csrc_nvboard/main.cpp
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@ -1,27 +1,38 @@
#include <cstdlib>
#include <VSegHandler.h>
#include <cassert>
#include <cstdlib>
#include <nvboard.h>
#include <verilated.h>
#include <verilated_vcd_c.h>
#include <nvboard.h>
#include <VSegHandler.h>
#ifndef VERILATOR_TOPMODULE
#define VERILATOR_TOPMODULE VSegHandler
#endif
const int MAX_SIM_TIME=100;
const int MAX_SIM_TIME = 100;
int keycode = 0;
void nvboard_bind_all_pins(VERILATOR_TOPMODULE* top);
static void single_cycle(VERILATOR_TOPMODULE* top) {
top->clock = 0; top->eval();
top->clock = 1; top->eval();
template <class F> void cycle(VERILATOR_TOPMODULE *top, F &&f) {
top->clock = 0;
top->eval();
f();
top->clock = 1;
top->eval();
}
static void reset(VERILATOR_TOPMODULE* top, int n) {
void nvboard_bind_all_pins(VERILATOR_TOPMODULE *top);
static void single_cycle(VERILATOR_TOPMODULE *top) {
top->clock = 0;
top->eval();
top->clock = 1;
top->eval();
}
static void reset(VERILATOR_TOPMODULE *top, int n) {
top->reset = 1;
while (n -- > 0) single_cycle(top);
while (n-- > 0)
single_cycle(top);
top->reset = 0;
}
@ -33,8 +44,12 @@ int main(int argc, char **argv, char **env) {
reset(top, 10);
while (true) {
nvboard_update();
top->eval();
single_cycle(top);
cycle(top, [&] {
if (keycode != top->io_keycode_bits) {
printf("%d\n", top->io_keycode_bits);
keycode = top->io_keycode_bits;
}
});
}
delete top;
}