> compile NEMU
ysyx_22040000 李心杨 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar 1 12:35:11 UTC 2024 x86_64 GNU/Linux 12:12:02 up 21:47, 2 users, load average: 0.54, 0.65, 1.33
This commit is contained in:
tracer-ysyx
parent
52573cf68e
commit
a50619438f
15 changed files with 402 additions and 198 deletions
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@ -14,8 +14,8 @@ jobs:
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submodules: true
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- name: Build abstract-machine
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run: |
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nix build .#abstract-machine
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nix build .?submodules=1#abstract-machine
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- name: Build nemu
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run: |
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nix build .#nemu
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nix build .?submodules=1#nemu
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@ -1,6 +1,6 @@
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cmake_minimum_required(VERSION 3.20)
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project(npc)
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project(flow)
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set (CMAKE_CXX_STANDARD 11)
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cmake_policy(SET CMP0144 NEW)
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@ -17,7 +17,7 @@ find_package(verilator REQUIRED)
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find_library(NVBOARD_LIBRARY NAMES nvboard)
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find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h)
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set(TOPMODULES "Switch" "Keyboard")
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set(TOPMODULES "Flow")
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foreach(TOPMODULE IN LISTS TOPMODULES)
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@ -58,7 +58,7 @@ foreach(TOPMODULE IN LISTS TOPMODULES)
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file(GLOB_RECURSE SOURCES csrc_nvboard/${TOPMODULE}/*.cpp)
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add_executable(V${TOPMODULE}_nvboard ${SOURCES} ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/auto_bind.cpp)
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verilate(V${TOPMODULE}_nvboard TRACE COVERAGE THREADS
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verilate(V${TOPMODULE}_nvboard TRACE THREADS
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TOP_MODULE ${TOPMODULE}
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PREFIX V${TOPMODULE}
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SOURCES ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc/${TOPMODULE}.v)
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3
npc/constr/Flow.nxdc
Normal file
3
npc/constr/Flow.nxdc
Normal file
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@ -0,0 +1,3 @@
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top=Flow
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io_clock(LD0)
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@ -2,14 +2,14 @@ ThisBuild / scalaVersion := "2.13.12"
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ThisBuild / version := "0.1.0"
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val chiselVersion = "5.1.0"
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val chiselVersion = "6.2.0"
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lazy val root = (project in file("."))
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.settings(
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name := "flow",
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libraryDependencies ++= Seq(
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"org.chipsalliance" %% "chisel" % chiselVersion,
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"edu.berkeley.cs" %% "chiseltest" % "5.0.2" % "test",
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"edu.berkeley.cs" %% "chiseltest" % "6.0.0" % "test",
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"com.chuusai" %% "shapeless" % "2.3.3"
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),
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scalacOptions ++= Seq(
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@ -20,4 +20,4 @@ lazy val root = (project in file("."))
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"-Ymacro-annotations",
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),
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addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full),
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)
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)
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@ -1,34 +1,63 @@
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package npc.util
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package flow.components
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import chisel3._
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import chisel3.util._
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import shapeless.{HNil, ::}
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class ALUGenerator(width: Int) extends Module {
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require(width >= 0)
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val io = IO(new Bundle {
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val a = Input(UInt(width.W))
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val b = Input(UInt(width.W))
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val op = Input(UInt(4.W))
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val out = Output(UInt(width.W))
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class ALUControlInterface extends Bundle {
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object OpSelect extends ChiselEnum {
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val aOpAdd, aOpSub, aOpNot, aOpAnd, aOpOr, aOpXor, aOpSlt, aOpEq, aOpNop = Value
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}
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object SrcSelect extends ChiselEnum {
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val aSrcRs1, aSrcImm = Value
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}
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val op = Input(OpSelect())
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val src = Input(SrcSelect())
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type CtrlTypes = OpSelect.Type :: SrcSelect.Type :: HNil
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def ctrlBindPorts: CtrlTypes = {
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op :: src :: HNil
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}
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}
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class ALU[T <: UInt](tpe: T) extends Module {
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val control = IO(new ALUControlInterface)
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val in = IO(new Bundle {
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val a = Input(Vec(control.SrcSelect.all.length, tpe))
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val b = Input(tpe)
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})
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val out = IO(new Bundle {
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val result = Output(tpe)
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})
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val adder_b = (Fill(width, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
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val add = io.a + adder_b
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val and = io.a & io.b
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val not = ~io.a
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val or = io.a | io.b
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val xor = io.a ^ io.b
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val slt = io.a < io.b
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val eq = io.a === io.b
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val a = in.a(control.src.asUInt)
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io.out := MuxLookup(io.op, 0.U)(Seq(
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0.U -> add,
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1.U -> add, // add with b reversed
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2.U -> not,
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3.U -> and,
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4.U -> or,
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5.U -> xor,
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6.U -> slt,
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7.U -> eq,
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// val adder_b = (Fill(tpe.getWidth, io.op(0)) ^ io.b) + io.op(0) // take (-b) if sub
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val add = a + in.b
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val sub = a - in.b
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val and = a & in.b
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val not = ~a
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val or = a | in.b
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val xor = a ^ in.b
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val slt = a < in.b
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val eq = a === in.b
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import control.OpSelect._
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out.result := MuxLookup(control.op, 0.U)(Seq(
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aOpAdd -> add,
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aOpSub -> sub,
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aOpNot -> not,
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aOpAnd -> and,
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aOpOr -> or,
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aOpXor -> xor,
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aOpSlt -> slt,
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aOpEq -> eq
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))
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}
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object ALU {
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def apply[T <: UInt](tpe: T): ALU[T] = {
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Module(new ALU(tpe))
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}
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}
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@ -1,44 +1,129 @@
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package npc
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package flow
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import scala.reflect.runtime.universe._
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import chisel3._
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import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
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import chisel3.util.{SRAM}
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import chisel3.util.experimental.decode.{decoder, TruthTable}
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import chisel3.stage.ChiselOption
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import npc.util.{ KeyboardSegController, RegisterFile }
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import flowpc.components.ProgramCounter
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import chisel3.util.log2Ceil
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import chisel3.util.BitPat
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import chisel3.util.Enum
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import chisel3.experimental.prefix
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import shapeless.{HNil, ::}
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import shapeless.HList
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import shapeless.ops.coproduct.Prepend
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import chisel3.util.{ BinaryMemoryFile, HexMemoryFile }
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class Switch extends Module {
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val io = IO(new Bundle {
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val sw = Input(Vec(2, Bool()))
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val out = Output(Bool())
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})
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io.out := io.sw(0) ^ io.sw(1)
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object RV32Inst {
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private val bp = BitPat
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val addi = this.bp("b???????_?????_?????_000_?????_00100_11")
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val inv = this.bp("b???????_?????_?????_???_?????_?????_??")
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}
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import npc.util.{PS2Port, KeyboardController, SegControllerGenerator}
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class Keyboard extends Module {
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val io = IO(new Bundle {
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val ps2 = PS2Port()
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val segs = Output(Vec(8, UInt(8.W)))
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})
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val seg_handler = Module(new KeyboardSegController)
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val keyboard_controller = Module(new KeyboardController)
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seg_handler.io.keycode <> keyboard_controller.io.out
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keyboard_controller.io.ps2 := io.ps2
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io.segs := seg_handler.io.segs
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class PcControl(width: Int) extends Bundle {
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object SrcSelect extends ChiselEnum {
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val pPC, pExeResult = Value
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}
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val srcSelect = Output(SrcSelect())
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}
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<<<<<<< Updated upstream
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=======
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class Flowpc extends Module {
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val io = IO(new Bundle { })
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val register_file = new RegisterFile(readPorts = 2);
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val pc = new ProgramCounter(32);
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val adder = new SRAM()
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import flow.components.{RegControl, PcControlInterface, ALUControlInterface}
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class Control(width: Int) extends Module {
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val inst = IO(Input(UInt(width.W)))
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val reg = IO(Flipped(new RegControl))
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val pc = IO(Flipped(new PcControlInterface))
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val alu = IO(Flipped(new ALUControlInterface))
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// TODO: Add .ctrlTypes together instead of writing them by hand.
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type T =
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Bool :: reg.WriteSelect.Type :: pc.SrcSelect.Type :: alu.OpSelect.Type :: alu.SrcSelect.Type :: HNil
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val dst: T = reg.ctrlBindPorts ++ pc.ctrlBindPorts ++ alu.ctrlBindPorts
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val dstList = dst.toList
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val reversePrefixSum = dstList.scanLeft(0)(_ + _.getWidth).reverse
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val slices = reversePrefixSum.zip(reversePrefixSum.tail)
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import reg.WriteSelect._
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import pc.SrcSelect._
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import alu.OpSelect._
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import alu.SrcSelect._
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import RV32Inst._
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val ControlMapping: Array[(BitPat, T)] = Array(
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// Regs :: PC :: Exe
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// writeEnable :: writeSelect :: srcSelect ::
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(addi, true.B :: rAluOut :: pStaticNpc :: aOpAdd :: aSrcImm :: HNil),
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)
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val default = BitPat.dontCare(dstList.map(_.getWidth).reduce(_ + _))
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def toBits(t: T): BitPat = {
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val list: List[Data] = t.toList
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list.map(x => BitPat(x.litValue.toInt.U(x.getWidth.W))).reduceLeft(_ ## _)
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}
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val out = decoder(
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inst,
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TruthTable(ControlMapping.map(it => (it._1 -> toBits(it._2))), default))
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val srcList = slices.map(s => out(s._1 - 1, s._2))
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srcList
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.zip(dstList.reverse)
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.foreach({ case (src, dst) =>
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dst := src.asTypeOf(dst)
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})
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}
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import flow.components.{RegisterFile, RegFileInterface, ProgramCounter, ALU}
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import chisel3.util.experimental.loadMemoryFromFileInline
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class Flow extends Module {
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val dataType = UInt(32.W)
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val ram = SRAM(
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size = 1024,
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tpe = dataType,
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numReadPorts = 2,
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numWritePorts = 1,
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numReadwritePorts = 0,
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memoryFile = HexMemoryFile("./resource/addi.txt")
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)
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val control = Module(new Control(32))
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val reg = RegisterFile(32, dataType, 2, 2)
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val pc = Module(new ProgramCounter(dataType))
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val alu = Module(new ALU(dataType))
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ram.readPorts(0).enable := true.B
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ram.readPorts(0).address := pc.out - 0x80000000L.U
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val inst = ram.readPorts(0).data
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import control.pc.SrcSelect._
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pc.in.pcSrcs(pStaticNpc.litValue.toInt) := pc.out + 4.U
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pc.in.pcSrcs(pBranchResult.litValue.toInt) := alu.out.result
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control.inst := inst
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reg.control <> control.reg
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pc.control <> control.pc
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alu.control <> control.alu
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import control.reg.WriteSelect._
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reg.in.writeData(rAluOut.litValue.toInt) := alu.out.result
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// TODO: Read address in load command goes here
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ram.readPorts(1).enable := false.B
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ram.readPorts(1).address := 0.U
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reg.in.writeData(rMemOut.litValue.toInt) := ram.readPorts(1).data
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reg.in.writeAddr := inst(11, 7)
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reg.in.rs(0) := inst(19, 15)
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reg.in.rs(1) := inst(24, 20)
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// TODO: Memory write goes here
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ram.writePorts(0).address := 1.U
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ram.writePorts(0).data := 1.U
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ram.writePorts(0).enable := false.B
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import control.alu.SrcSelect._
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alu.in.a(aSrcRs1.litValue.toInt) := reg.out.src(0)
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alu.in.a(aSrcImm.litValue.toInt) := inst(31, 20)
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alu.in.b := reg.out.src(1)
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dontTouch(control.out)
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}
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>>>>>>> Stashed changes
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@ -1,11 +1,39 @@
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package flowpc.components
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package flow.components
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import chisel3._
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import chisel3.util.{Valid}
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import chisel3.util.{Valid, log2Ceil}
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import chisel3.util.MuxLookup
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import shapeless.{HNil, ::}
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class ProgramCounter (width: Int) extends Module {
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val io = new Bundle {
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val next_pc = Input(Flipped(Valid(UInt(width.W))))
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val pc = Output(UInt(width.W))
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class PcControlInterface extends Bundle {
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object SrcSelect extends ChiselEnum {
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val pStaticNpc, pBranchResult = Value
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}
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val srcSelect = Input(SrcSelect())
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type CtrlTypes = SrcSelect.Type :: HNil
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def ctrlBindPorts: CtrlTypes = {
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srcSelect :: HNil
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}
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}
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class ProgramCounter[T <: Data](tpe: T) extends Module {
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val control = IO(new PcControlInterface)
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val in = IO(new Bundle {
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val pcSrcs = Input(Vec(control.SrcSelect.all.length, tpe))
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})
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val out = IO(Output(tpe))
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private val pc = RegInit(0x80000000L.U)
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pc := in.pcSrcs(control.srcSelect.asUInt)
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out := pc
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}
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object ProgramCounter {
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def apply[T <: Data](tpe: T): ProgramCounter[T] = {
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val pc = Module(new ProgramCounter(tpe))
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pc
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}
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io.pc := Mux(io.next_pc.valid, io.next_pc.bits, io.pc)
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}
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@ -1,17 +1,23 @@
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package flowpc.components
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package flow.components
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import chisel3._
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import chisel3.util.log2Ceil
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import chisel3.util.UIntToOH
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import chisel3.util.MuxLookup
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import shapeless.{ HNil, :: }
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class RegControl extends Bundle {
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val writeEnable = Input(Bool())
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object WriteSelect extends ChiselEnum {
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val rAluOut, rMemOut = Value
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}
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val writeEnable = Input(Bool())
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val writeSelect = Input(WriteSelect())
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type CtrlTypes = Bool :: WriteSelect.Type :: HNil
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def ctrlBindPorts: CtrlTypes = {
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writeEnable :: writeSelect :: HNil
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}
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}
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class RegFileData[T <: Data](size:Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
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@ -27,7 +33,15 @@ class RegFileData[T <: Data](size:Int, tpe: T, numReadPorts: Int, numWritePorts:
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class RegFileInterface[T <: Data](size: Int, tpe: T, numReadPorts: Int, numWritePorts: Int) extends Bundle {
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val control = new RegControl
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val data = new RegFileData(size, tpe, numReadPorts, numWritePorts)
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// val data = new RegFileData(size, tpe, numReadPorts, numWritePorts)
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val in = new Bundle {
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val writeAddr = Input(UInt(size.W))
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val writeData = Input(Vec(numWritePorts, tpe))
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val rs = Input(Vec(numReadPorts, UInt(size.W)))
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}
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val out = new Bundle {
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val src = Output(Vec(numReadPorts, tpe))
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}
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}
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class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends Module {
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@ -52,6 +66,7 @@ class RegisterFileCore[T <: Data](size: Int, tpe: T, numReadPorts: Int) extends
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for (readPort <- readPorts) {
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readPort.data := regFile(readPort.addr)
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}
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dontTouch(regFile)
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}
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object RegisterFile {
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@ -60,13 +75,11 @@ object RegisterFile {
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val _out = Wire(new RegFileInterface(size, tpe, numReadPorts, numWritePorts))
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val clock = core.clock
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for (i <- 0 until numReadPorts) {
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core.readPorts(i).addr := _out.data.read(i).rs
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_out.data.read(i).src := core.readPorts(i).data
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core.readPorts(i).addr := _out.in.rs(i)
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_out.out.src(i) := core.readPorts(i).data
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}
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core.writePort.addr := _out.data.write.addr
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core.writePort.data := MuxLookup(_out.control.writeSelect, 0.U)(
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_out.control.WriteSelect.all.map(x => (x -> _out.data.write.data(x.asUInt).asUInt))
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)
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core.writePort.addr := _out.in.writeAddr
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core.writePort.data := _out.in.writeData(_out.control.writeSelect.asUInt)
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core.writePort.enable := _out.control.writeEnable
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_out
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}
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@ -1,105 +1,47 @@
|
|||
package npc
|
||||
package flow
|
||||
|
||||
import chisel3._
|
||||
import chiseltest._
|
||||
import org.scalatest.freespec.AnyFreeSpec
|
||||
import chiseltest.simulator.WriteVcdAnnotation
|
||||
|
||||
import npc.util._
|
||||
import flow.Flow
|
||||
|
||||
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
|
||||
"RegisterFile should work" - {
|
||||
"with 2 read ports" in {
|
||||
test(new RegisterFile(2)) { c =>
|
||||
def readExpect(addr: Int, value: Int, port: Int = 0): Unit = {
|
||||
c.io.readAddr(port).poke(addr.U)
|
||||
c.io.readData(port).expect(value.U)
|
||||
}
|
||||
def write(addr: Int, value: Int): Unit = {
|
||||
c.io.writeEnable.poke(true.B)
|
||||
c.io.writeData.poke(value.U)
|
||||
c.io.writeAddr.poke(addr.U)
|
||||
class RV32CPUSpec extends AnyFreeSpec with ChiselScalatestTester {
|
||||
"MemoryFile" - {
|
||||
"correctly load" in {
|
||||
import chisel3.util.{SRAM, SRAMInterface, HexMemoryFile}
|
||||
class UserMem extends Module {
|
||||
val io = IO(new SRAMInterface(1024, UInt(32.W), 1, 1, 0))
|
||||
val memoryFile = HexMemoryFile("../resource/addi.txt")
|
||||
io :<>= SRAM(
|
||||
size = 1024,
|
||||
tpe = UInt(32.W),
|
||||
numReadPorts = 1,
|
||||
numWritePorts = 1,
|
||||
numReadwritePorts = 0,
|
||||
memoryFile = memoryFile
|
||||
)
|
||||
|
||||
val read = io.readPorts(0).data
|
||||
printf(cf"memoryFile=$memoryFile, readPort=$read%x\n")
|
||||
}
|
||||
test(new UserMem).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
|
||||
c.io.readPorts(0).enable.poke(true.B)
|
||||
c.io.writePorts(0).enable.poke(false.B)
|
||||
c.io.writePorts(0).address.poke(0.U)
|
||||
c.io.writePorts(0).data.poke(0.U)
|
||||
for (i <- 0 until 32) {
|
||||
c.io.readPorts(0).address.poke(i.U)
|
||||
c.clock.step(1)
|
||||
c.io.writeEnable.poke(false.B)
|
||||
}
|
||||
// everything should be 0 on init
|
||||
for (i <- 0 until 32) {
|
||||
readExpect(i, 0, port = 0)
|
||||
readExpect(i, 0, port = 1)
|
||||
}
|
||||
|
||||
// write 5 * addr + 3
|
||||
for (i <- 0 until 32) {
|
||||
write(i, 5 * i + 3)
|
||||
}
|
||||
|
||||
// check that the writes worked
|
||||
for (i <- 0 until 32) {
|
||||
readExpect(i, if (i == 0) 0 else 5 * i + 3, port = i % 2)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
|
||||
"With 32 width, " - {
|
||||
val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
|
||||
val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
|
||||
val mask = BigInt("FFFFFFFF", 16)
|
||||
val oprands: List[(BigInt, BigInt)] = List(
|
||||
(5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
|
||||
)
|
||||
val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
|
||||
0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
|
||||
1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
|
||||
2 -> ((a, _) => not(a)),
|
||||
3 -> (_ & _),
|
||||
4 -> (_ | _),
|
||||
5 -> (_ ^ _),
|
||||
6 -> ((a, b) => if (a < b) 1 else 0),
|
||||
7 -> ((a, b) => if (a == b) 1 else 0),
|
||||
)
|
||||
val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
|
||||
c.io.op.poke(op.U)
|
||||
oprands.foreach({ case (a, b) =>
|
||||
c.io.a.poke(a.U)
|
||||
c.io.b.poke(b.U)
|
||||
c.io.out.expect(operations(op)(a, b))
|
||||
})
|
||||
}
|
||||
"add should work" in {
|
||||
test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
|
||||
}
|
||||
"sub should work" - {
|
||||
"with positive result" in {
|
||||
test(new ALUGenerator(32)) { c =>
|
||||
validate(c, 1, oprands.filter({case (a, b) => a >= b}))
|
||||
}
|
||||
}
|
||||
"with negative result" in {
|
||||
test(new ALUGenerator(32)) { c =>
|
||||
validate(c, 1, oprands.filter({case (a, b) => a < b}))
|
||||
}
|
||||
}
|
||||
}
|
||||
"not should work" in {
|
||||
test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
|
||||
}
|
||||
"and should work" in {
|
||||
test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
|
||||
}
|
||||
"or should work" in {
|
||||
test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
|
||||
}
|
||||
"xor should work" in {
|
||||
test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
|
||||
}
|
||||
"compare should work" in {
|
||||
test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
|
||||
}
|
||||
"equal should work" in {
|
||||
test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
|
||||
"should compile" in {
|
||||
test(new Flow) { c =>
|
||||
c.clock.step(1)
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
package flowpc
|
||||
package flow
|
||||
|
||||
import chisel3._
|
||||
import chiseltest._
|
||||
import org.scalatest.freespec.AnyFreeSpec
|
||||
import chiseltest.simulator.WriteVcdAnnotation
|
||||
|
||||
import flowpc.components._
|
||||
import flow.components._
|
||||
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
|
||||
"RegisterFileCore" - {
|
||||
"register 0 is always 0" in {
|
||||
|
|
@ -41,22 +41,40 @@ class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
|
|||
}
|
||||
}
|
||||
"RegisterInterface" - {
|
||||
"worked" in {
|
||||
class Top extends Module {
|
||||
val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2))
|
||||
val rf = RegisterFile(32, UInt(32.W), 2, 2)
|
||||
io :<>= rf
|
||||
}
|
||||
class Top extends Module {
|
||||
val io = IO(new RegFileInterface(32, UInt(32.W), 2, 2))
|
||||
val rf = RegisterFile(32, UInt(32.W), 2, 2)
|
||||
io :<>= rf
|
||||
}
|
||||
"write" in {
|
||||
test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
|
||||
import c.io.control.WriteSelect._
|
||||
val writePort = rAluOut.litValue.toInt
|
||||
c.io.control.writeEnable.poke(true)
|
||||
c.io.control.writeSelect.poke(rAluOut)
|
||||
c.io.data.write.addr.poke(5)
|
||||
c.io.data.write.data(writePort).poke(0xcdef)
|
||||
c.io.data.read(0).rs.poke(5)
|
||||
c.io.in.writeAddr.poke(5)
|
||||
c.io.in.writeData(writePort).poke(0xcdef)
|
||||
c.io.in.rs(0).poke(5)
|
||||
c.clock.step(1)
|
||||
c.io.data.read(0).src.expect(0xcdef)
|
||||
c.io.out.src(0).expect(0xcdef)
|
||||
}
|
||||
}
|
||||
"no data is written when not enabled" in {
|
||||
test(new Top).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
|
||||
import c.io.control.WriteSelect._
|
||||
val writePort = rAluOut.litValue.toInt
|
||||
c.io.control.writeEnable.poke(true)
|
||||
c.io.control.writeSelect.poke(rAluOut)
|
||||
c.io.in.writeAddr.poke(5)
|
||||
c.io.in.writeData(writePort).poke(0xcdef)
|
||||
c.io.in.rs(0).poke(5)
|
||||
c.clock.step(1)
|
||||
|
||||
c.io.control.writeEnable.poke(false)
|
||||
c.io.in.writeData(writePort).poke(0x1234)
|
||||
c.clock.step(1)
|
||||
|
||||
c.io.out.src(0).expect(0xcdef)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
43
npc/csrc/Flow/main.cpp
Normal file
43
npc/csrc/Flow/main.cpp
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
#include <cstdlib>
|
||||
#include <cassert>
|
||||
#include <cstdlib>
|
||||
#include <verilated.h>
|
||||
#include <verilated_vcd_c.h>
|
||||
#include <VFlow.h>
|
||||
#define MAX_SIM_TIME 100
|
||||
#define VERILATOR_TRACE
|
||||
|
||||
int main(int argc, char **argv, char **env) {
|
||||
int sim_time = 0;
|
||||
Verilated::commandArgs(argc, argv);
|
||||
|
||||
VFlow *top = new VFlow;
|
||||
|
||||
Verilated::traceEverOn(true);
|
||||
VerilatedVcdC *m_trace = new VerilatedVcdC;
|
||||
#ifdef VERILATOR_TRACE
|
||||
top->trace(m_trace, 5);
|
||||
m_trace->open("waveform.vcd");
|
||||
#endif
|
||||
for (sim_time = 0; sim_time < 10; sim_time++) {
|
||||
top->eval();
|
||||
top->clock = !top->clock;
|
||||
top->reset = 1;
|
||||
#ifdef VERILATOR_TRACE
|
||||
m_trace->dump(sim_time);
|
||||
#endif
|
||||
}
|
||||
top->reset = 0;
|
||||
for (sim_time = 10; sim_time < MAX_SIM_TIME; sim_time++) {
|
||||
top->eval();
|
||||
top->clock = !top->clock;
|
||||
#ifdef VERILATOR_TRACE
|
||||
m_trace->dump(sim_time);
|
||||
#endif
|
||||
}
|
||||
#ifdef VERILATOR_TRACE
|
||||
m_trace->close();
|
||||
#endif
|
||||
delete top;
|
||||
exit(EXIT_SUCCESS);
|
||||
}
|
||||
12
npc/csrc_nvboard/Flow/main.cpp
Normal file
12
npc/csrc_nvboard/Flow/main.cpp
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#include <verilated.h>
|
||||
#include <verilated_vcd_c.h>
|
||||
// #include <nvboard.h>
|
||||
#include <VFlow.h>
|
||||
|
||||
const int MAX_SIM_TIME=100;
|
||||
|
||||
// void nvboard_bind_all_pins(VFLow* top);
|
||||
|
||||
int main(int argc, char **argv, char **env) {
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -5,11 +5,11 @@
|
|||
"systems": "systems"
|
||||
},
|
||||
"locked": {
|
||||
"lastModified": 1701680307,
|
||||
"narHash": "sha256-kAuep2h5ajznlPMD9rnQyffWG8EM/C73lejGofXvdM8=",
|
||||
"lastModified": 1710146030,
|
||||
"narHash": "sha256-SZ5L6eA7HJ/nmkzGG7/ISclqe6oZdOZTNoesiInkXPQ=",
|
||||
"owner": "numtide",
|
||||
"repo": "flake-utils",
|
||||
"rev": "4022d587cbbfd70fe950c1e2083a02621806a725",
|
||||
"rev": "b1d9ab70662946ef0850d488da1c9019f3a9752a",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
|
|
@ -20,11 +20,11 @@
|
|||
},
|
||||
"nixpkgs": {
|
||||
"locked": {
|
||||
"lastModified": 1704194953,
|
||||
"narHash": "sha256-RtDKd8Mynhe5CFnVT8s0/0yqtWFMM9LmCzXv/YKxnq4=",
|
||||
"lastModified": 1709961763,
|
||||
"narHash": "sha256-6H95HGJHhEZtyYA3rIQpvamMKAGoa8Yh2rFV29QnuGw=",
|
||||
"owner": "NixOS",
|
||||
"repo": "nixpkgs",
|
||||
"rev": "bd645e8668ec6612439a9ee7e71f7eac4099d4f6",
|
||||
"rev": "3030f185ba6a4bf4f18b87f345f104e6a6961f34",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
|
|
@ -34,6 +34,22 @@
|
|||
"type": "github"
|
||||
}
|
||||
},
|
||||
"nixpkgs-circt162": {
|
||||
"locked": {
|
||||
"lastModified": 1705645507,
|
||||
"narHash": "sha256-tX3vipIAmNDBA8WNWG4oY4KyTfnm2YieTHO2BhG8ISA=",
|
||||
"owner": "NixOS",
|
||||
"repo": "nixpkgs",
|
||||
"rev": "7995cae3ad60e3d6931283d650d7f43d31aaa5c7",
|
||||
"type": "github"
|
||||
},
|
||||
"original": {
|
||||
"owner": "NixOS",
|
||||
"repo": "nixpkgs",
|
||||
"rev": "7995cae3ad60e3d6931283d650d7f43d31aaa5c7",
|
||||
"type": "github"
|
||||
}
|
||||
},
|
||||
"nur-xin": {
|
||||
"inputs": {
|
||||
"nixpkgs": [
|
||||
|
|
@ -41,11 +57,11 @@
|
|||
]
|
||||
},
|
||||
"locked": {
|
||||
"lastModified": 1704450168,
|
||||
"narHash": "sha256-zOLL35LX83Of64quCyxpyP8rTSO/tgrfHNm52tFo6VU=",
|
||||
"lastModified": 1707020873,
|
||||
"narHash": "sha256-+dNltc7tjgTIyle/I/5siQ5IvPwu+R5Uf6e24CmjLNk=",
|
||||
"ref": "refs/heads/master",
|
||||
"rev": "beda2a57d946f392d958755c7bb03ac092a20f42",
|
||||
"revCount": 140,
|
||||
"rev": "8142717e7154dbaadee0679f0224fe75cebb1735",
|
||||
"revCount": 147,
|
||||
"type": "git",
|
||||
"url": "https://git.xinyang.life/xin/nur.git"
|
||||
},
|
||||
|
|
@ -58,6 +74,7 @@
|
|||
"inputs": {
|
||||
"flake-utils": "flake-utils",
|
||||
"nixpkgs": "nixpkgs",
|
||||
"nixpkgs-circt162": "nixpkgs-circt162",
|
||||
"nur-xin": "nur-xin"
|
||||
}
|
||||
},
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
{
|
||||
inputs = {
|
||||
nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
|
||||
nixpkgs-circt162.url = "github:NixOS/nixpkgs/7995cae3ad60e3d6931283d650d7f43d31aaa5c7";
|
||||
flake-utils.url = "github:numtide/flake-utils";
|
||||
nur-xin = {
|
||||
url = "git+https://git.xinyang.life/xin/nur.git";
|
||||
|
|
@ -11,14 +12,17 @@
|
|||
outputs = { self, ... }@inputs: with inputs;
|
||||
flake-utils.lib.eachDefaultSystem (system:
|
||||
let
|
||||
pkgs = nixpkgs.legacyPackages.${system} //
|
||||
pkgs = import nixpkgs { inherit system; config.allowUnfree = true; }//
|
||||
{ nur.xin = nur-xin.legacyPackages.${system}; };
|
||||
in
|
||||
{
|
||||
devShells.default = with pkgs; mkShell {
|
||||
CHISEL_FIRTOOL_PATH = "${nixpkgs-circt162.legacyPackages.${system}.circt}/bin";
|
||||
packages = [
|
||||
clang-tools
|
||||
rnix-lsp
|
||||
# rnix-lsp
|
||||
coursier
|
||||
espresso
|
||||
|
||||
gdb
|
||||
jre
|
||||
|
|
@ -36,7 +40,7 @@
|
|||
cmake
|
||||
sbt
|
||||
nur.xin.nvboard
|
||||
self.packages.${system}.circt
|
||||
nixpkgs-circt162.legacyPackages.${system}.circt
|
||||
yosys
|
||||
];
|
||||
buildInputs = [
|
||||
|
|
|
|||
10
npc/resource/addi.txt
Normal file
10
npc/resource/addi.txt
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
00114113
|
||||
00114113
|
||||
00114113
|
||||
00114113
|
||||
00114113
|
||||
00114113
|
||||
00114113
|
||||
00114113
|
||||
00114113
|
||||
00114113
|
||||
Loading…
Reference in a new issue