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> trace RTL

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ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 20:10:23  up  23:08,  2 users,  load average: 0.72, 0.68, 0.62
This commit is contained in:
tracer-ysyx 2023-12-23 20:10:23 +08:00 committed by xinyangli
parent fce7b3fcb3
commit a1624036d1
1 changed files with 4 additions and 2 deletions
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6
npc/Makefile
View file

@ -2,6 +2,7 @@ VSRC := $(wildcard vsrc/*.v)
CPPSRC := $(addprefix $(PWD)/,$(wildcard csrc/*.cpp))
PREFIX ?= build
OBJDIR := $(PREFIX)/obj
VERILATOR_FLAGS := --cc --exe
all: $(OBJDIR)
$(MAKE) -j -C $(OBJDIR) -f Vexample.mk Vexample
@ -10,8 +11,9 @@ sim: all
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================"
@$(OBJDIR)/Vexample +trace off
@$(OBJDIR)/Vexample +tracing_off
trace: VERILATOR_FLAGS += --trace
trace: all
$(call git_commit, "trace RTL") # DO NOT REMOVE THIS LINE!!!
@$(OBJDIR)/Vexample
@ -19,7 +21,7 @@ trace: all
$(OBJDIR): $(VSRC) $(CPPSRC)
mkdir -p $(OBJDIR)
verilator --trace --cc --exe --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
verilator $(VERILATOR_FLAGS) --Mdir $(PWD)/$(OBJDIR) $(VSRC) $(CPPSRC)
include ../Makefile