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refactor: move to dpi module for memory access

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This commit is contained in:
xinyangli 2024-04-03 22:39:33 +08:00
parent a478ef7639
commit 97cf418c86
Signed by: xin
SSH key fingerprint: SHA256:qZ/tzd8lYRtUFSrfBDBMcUqV4GHKxqeqRA3huItgvbk
15 changed files with 443 additions and 207 deletions
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1
.gitignore vendored
View file

@ -12,3 +12,4 @@
/nvboard
**/.cache
**/result
/.pre-commit-config.yaml

2
npc/.clang-format Normal file
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@ -0,0 +1,2 @@
---
BasedOnStyle: LLVM

1
npc/.gitignore vendored
View file

@ -15,3 +15,4 @@ hs_err_pid*
.vscode/
.direnv/
compile_commands.json

8
npc/CMakeLists.txt
View file

@ -30,6 +30,7 @@ if(BUILD_SIM_NVBOARD_TARGET)
find_package(SDL2 REQUIRED)
find_package(SDL2_image REQUIRED)
endif()
find_package(CLI11 CONFIG REQUIRED)
find_library(NVBOARD_LIBRARY NAMES nvboard)
find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h)
@ -52,8 +53,8 @@ set(CHISEL_EMIT_ARGS "--target-dir ${CHISEL_OUTPUT_TMP_DIR}")
# as we don't know if the result files will be different from cmake
# NOTE: Must reconfigure if we add new files in SCALA_CORE directory
file(GLOB_RECURSE SCALA_CORE_SOURCES "${SCALA_CORE}/src/main/scala/*.scala")
file(GLOB_RECURSE SCALA_CORE_RESOURCES "${SCALA_CORE}/src/resource/*")
set(CHISEL_DEPENDENCY ${SCALA_CORE_SOURCES} ${SCALA_CORE_RESOURCE} ${SCALA_CORE}/build.sbt)
file(GLOB_RECURSE SCALA_CORE_RESOURCES "${SCALA_CORE}/src/main/resource/*")
set(CHISEL_DEPENDENCY ${SCALA_CORE_SOURCES} ${SCALA_CORE_RESOURCES} ${SCALA_CORE}/build.sbt)
if(BUILD_USE_BLOOP)
set(CHISEL_TARGET bloop_${TOPMODULE})
@ -105,7 +106,7 @@ if(NOT EXISTS ${CHISEL_OUTPUT_TOPMODULE})
WORKING_DIRECTORY ${SCALA_CORE}
)
execute_process(
COMMAND ${CMAKE_COMMAND} -E copy_directory_if_different ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR}
COMMAND ${CMAKE_COMMAND} -E copy_directory ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR}
)
endif()
@ -144,7 +145,6 @@ verilate(V${TOPMODULE} TRACE COVERAGE THREADS
INCLUDE_DIRS ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc
VERILATOR_ARGS
"--vpi" # Enable VPI
)

24
npc/core/src/main/resources/RamDpi.v Normal file
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@ -0,0 +1,24 @@
import "DPI-C" function int pmem_read(input int addr);
import "DPI-C" function void pmem_write(input int waddr, input int wdata, input byte wmask);
module RamDpi (
input writeEnable,
input valid,
input [31:0] writeAddr,
input [31:0] writeData,
input [3:0] writeMask,
input reg [31:0] readAddr,
output reg [31:0] readData
);
always @(*) begin
if (valid) begin // 有读写请求时
readData = pmem_read(readAddr);
if (writeEnable) begin // 有写请求时
pmem_write(writeAddr, writeData, { 4'h0, writeMask });
end
end
else begin
readData = 0;
end
end
endmodule

31
npc/core/src/main/scala/FlowMain.scala
View file

@ -74,27 +74,18 @@ class Control(width: Int) extends Module {
})
}
import flow.components.{RegisterFile, ProgramCounter, ALU}
import flow.components.{RegisterFile, ProgramCounter, ALU, RamDpi}
import chisel3.util.experimental.loadMemoryFromFileInline
class Flow extends Module {
val dataType = UInt(32.W)
val ram = SRAM(
size = 1024,
tpe = dataType,
numReadPorts = 2,
numWritePorts = 1,
numReadwritePorts = 0,
memoryFile = HexMemoryFile("./resource/addi.txt")
)
val ram = Module(new RamDpi)
val control = Module(new Control(32))
val reg = Module(new RegisterFile(dataType, 32, 2))
val pc = Module(new ProgramCounter(dataType))
val alu = Module(new ALU(dataType))
ram.readPorts(0).enable := true.B
ram.readPorts(0).address := pc.out - 0x80000000L.U
val inst = ram.readPorts(0).data
ram.io.readAddr := pc.out
val inst = ram.io.readData
Trace.traceName(reg.control.writeEnable)
dontTouch(reg.control.writeEnable)
@ -111,18 +102,20 @@ class Flow extends Module {
import control.reg.WriteSelect._
reg.in.writeData(rAluOut.litValue.toInt) := alu.out.result
// TODO: Read address in load command goes here
ram.readPorts(1).enable := false.B
ram.readPorts(1).address := 0.U
reg.in.writeData(rMemOut.litValue.toInt) := ram.readPorts(1).data
reg.in.writeData(rMemOut.litValue.toInt) := DontCare
reg.in.writeAddr := inst(11, 7)
reg.in.rs(0) := inst(19, 15)
reg.in.rs(1) := inst(24, 20)
// TODO: Memory write goes here
ram.writePorts(0).address := 1.U
ram.writePorts(0).data := 1.U
ram.writePorts(0).enable := false.B
ram.io.writeAddr := DontCare
ram.io.writeData := DontCare
ram.io.writeMask := DontCare
ram.io.writeEnable := false.B
ram.io.valid := true.B
import control.alu.SrcSelect._
alu.in.a(aSrcRs1.litValue.toInt) := reg.out.src(0)

23
npc/core/src/main/scala/Mem.scala
View file

@ -1 +1,24 @@
package flow.components
import chisel3._
import chisel3.util.HasBlackBoxPath
import chisel3.util.HasBlackBoxResource
import chisel3.util.log2Ceil
import chisel3.experimental.noPrefix
import scala.collection.SeqMap
import javax.swing.plaf.synth.SynthRadioButtonMenuItemUI
class RamInterface[T <: Data](tpe: T, addrWidth: Int) extends Bundle {
val valid = Input(Bool())
val writeEnable = Input(Bool())
val writeAddr = Input(UInt(addrWidth.W))
val writeData = Input(tpe)
val writeMask = Input(UInt((addrWidth / 8).W))
val readAddr = Input(UInt(addrWidth.W))
val readData = Output(tpe)
}
class RamDpi extends BlackBox with HasBlackBoxResource {
val io = IO(new RamInterface(UInt(32.W), 32))
addResource("/RamDpi.v")
}

2
npc/core/src/main/scala/RegisterFile.scala
View file

@ -25,7 +25,7 @@ class RegControl extends Bundle {
class RegisterFile[T <: Data](tpe: T, regCount: Int, numReadPorts: Int) extends Module {
require(numReadPorts >= 0)
val control = IO(new RegControl)
val dataAddrWidth = log2Ceil(tpe.getWidth).W
val dataAddrWidth = log2Ceil(regCount).W
val in = IO(new Bundle {
val writeAddr = Input(UInt(dataAddrWidth))
val writeData = Input(Vec(control.WriteSelect.all.length, tpe))

101
npc/csrc/Flow/components.hpp Normal file
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@ -0,0 +1,101 @@
#ifndef _NPC_COMPONENTS_H_
#define _NPC_COMPONENTS_H_
#include <array>
#include <filesystem>
#include <fstream>
#include <verilated_vpi.h>
template <typename T, std::size_t nr> class _RegistersBase {
std::array<T, nr> regs;
virtual T fetch_reg(std::size_t id);
public:
void update() {
for (int i = 0; i < regs.size(); i++) {
regs[i] = fetch_reg(i);
}
}
void print_regs() {
for (int i = 0; i < regs.size(); i++) {
printf("%d: %d\t", i, regs[i]);
if (i % 8 == 7)
putchar('\n');
}
putchar('\n');
}
};
template <typename T, std::size_t nr>
class _RegistersVPI : public _RegistersBase<T, nr> {
std::array<vpiHandle, nr> reg_handles;
T fetch_reg(std::size_t id) {
s_vpi_value v;
v.format = vpiIntVal;
vpi_get_value(reg_handles[id], &v);
return v.value.integer;
}
public:
_RegistersVPI<T, nr>(const std::string regs_prefix) {
for (int i = 0; i < nr; i++) {
std::string regname = regs_prefix + std::to_string(i);
vpiHandle vh = vpi_handle_by_name((PLI_BYTE8 *)regname.c_str(), NULL);
reg_handles[i] = vh;
}
}
};
template <typename T, std::size_t n> class Memory {
std::array<T, n> mem;
std::size_t addr_to_index(std::size_t addr) {
if (addr < 0x80000000) {
return 0;
}
// Linear mapping
return (addr >> 2) - 0x20000000;
}
uint32_t expand_bits(uint8_t bits) {
uint32_t x = bits;
x = (x | (x << 7) | (x << 14) | (x << 21)) & 0x01010101;
x = x * 0xFF;
// printf("expand: %hhx->%x\n", bits, x);
return x;
}
public:
Memory(std::filesystem::path filepath, bool is_binary = true) {
assert(std::filesystem::exists(filepath));
if (is_binary) {
std::ifstream file(filepath, std::ios::binary);
char *pmem = reinterpret_cast<char *>(mem.data());
file.read(pmem, mem.size() / sizeof(mem[0]));
} else {
std::string line;
std::ifstream file(filepath);
int i = 0;
while (std::getline(file, line)) {
mem[i++] = std::stoul(line, 0, 16);
}
}
}
const T &operator[](std::size_t addr) { return this->read(addr); }
/**
* Always reads and returns 4 bytes from the address raddr & ~0x3u.
*/
T read(int raddr) {
printf("raddr: 0x%x\n", raddr);
return mem[addr_to_index((uint32_t)raddr)];
}
/**
* Always writes to the 4 bytes at the address `waddr` & ~0x3u.
* Each bit in `wmask` represents a mask for one byte in wdata.
* For example, wmask = 0x3 means only the lowest 2 bytes are written,
* and the other bytes in memory remain unchanged.
*/
void write(int waddr, T wdata, char wmask) {
printf("waddr: 0x%x\n", waddr);
mem[addr_to_index((uint32_t)waddr)] = expand_bits(wmask) & wdata;
}
};
#endif

27
npc/csrc/Flow/config.cpp Normal file
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@ -0,0 +1,27 @@
#include "config.hpp"
void Config::cli_parse(int argc, char **argv) {
CLI::App app;
app.add_option("-m,--memory", memory_file, "Content of memory")
->required()
->check(CLI::ExistingFile);
app.add_flag("!--no-bin", memory_file_binary,
"Memory file is in text format");
app.add_flag("--trace", do_trace, "Enable tracing");
app.add_option("--wav", wavefile, "output .vcd file path")
->check([this](const std::string &) {
if (!this->do_trace)
throw CLI::ValidationError(
"dependency", "You must turn on trace before specify wave file");
return std::string();
});
app.add_option("-t", max_sim_time, "Max simulation timestep");
try {
app.parse(argc, argv);
} catch (const CLI::ParseError &e) {
exit((app).exit(e));
}
}
Config config;

19
npc/csrc/Flow/config.hpp Normal file
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@ -0,0 +1,19 @@
#ifndef _NPC_CONFIG_H_
#define _NPC_CONFIG_H_
#include <CLI/App.hpp>
#include <CLI/CLI.hpp>
#include <CLI/Validators.hpp>
#include <filesystem>
struct Config {
std::filesystem::path wavefile;
std::filesystem::path memory_file;
uint64_t max_sim_time = 1000;
bool memory_file_binary = {true};
bool do_trace{false};
void cli_parse(int argc, char **argv);
};
extern Config config;
#endif

196
npc/csrc/Flow/main.cpp
View file

@ -1,189 +1,39 @@
#include <array>
#include <cstddef>
#include <cstdint>
#include <filesystem>
#include <sys/types.h>
#include <vpi_user.h>
#include "components.hpp"
#include "config.hpp"
#include "vl_wrapper.hpp"
#include <VFlow.h>
#include <cstdlib>
#include <memory>
#include <verilated.h>
#include <verilated_vcd_c.h>
#include <verilated_vpi.h>
#include <string>
#define MAX_SIM_TIME 100
#define VERILATOR_TRACE
template <class T>
class Tracer {
#ifdef VERILATOR_TRACE
std::shared_ptr<T> top;
std::unique_ptr<VerilatedVcdC> m_trace;
uint64_t cycle = 0;
#endif
public:
Tracer(T *top, std::filesystem::path wavefile) {
#ifdef VERILATOR_TRACE
top = top;
Verilated::traceEverOn(true);
m_trace = std::make_unique<VerilatedVcdC>();
top->trace(m_trace.get(), 5);
m_trace->open(wavefile.c_str());
#endif
}
~Tracer() {
#ifdef VERILATOR_TRACE
m_trace->close();
#endif
}
/**
* Dump signals to waveform file. Must be called once after every top->eval() call.
*/
void update() {
#ifdef VERILATOR_TRACE
m_trace->dump(cycle++);
#endif
}
};
template <typename T, std::size_t nr>
class _RegistersBase {
std::array<T, nr> regs;
virtual T fetch_reg(size_t id);
public:
void update() {
for(int i = 0; i < regs.size(); i++) {
regs[i] = fetch_reg(i);
}
}
void print_regs() {
for(int i = 0; i < regs.size(); i++) {
printf("%d: %d\t", i, regs[i]);
if(i % 8 == 7) putchar('\n');
}
putchar('\n');
}
};
template <typename T, std::size_t nr>
class _RegistersVPI : public _RegistersBase<T, nr> {
std::array<vpiHandle, nr> reg_handles;
T fetch_reg(size_t id) {
s_vpi_value v;
v.format = vpiIntVal;
vpi_get_value(reg_handles[id], &v);
return v.value.integer;
}
public:
_RegistersVPI<T, nr>(const std::string regs_prefix) {
for(int i = 0; i < nr; i++) {
std::string regname = regs_prefix + std::to_string(i);
vpiHandle vh = vpi_handle_by_name((PLI_BYTE8 *)regname.c_str(), NULL);
reg_handles[i] = vh;
}
}
};
typedef _RegistersVPI<uint32_t, 32> Registers;
template <typename T, std::size_t n>
class Memory {
std::array<T, n> mem;
size_t addr_to_index(size_t addr) {
// Linear mapping
return (addr >> 2) - 0x20000000;
}
uint32_t expand_bits(uint8_t bits) {
uint32_t x = bits;
x = (x | (x << 7) | (x << 14) | (x << 21)) & 0x01010101;
x = x * 0xFF;
// printf("expand: %hhx->%x\n", bits, x);
return x;
}
public:
const T& operator[](size_t addr) {
return this->read(addr);
}
/**
* Always reads and returns 4 bytes from the address raddr & ~0x3u.
*/
T read(int raddr) {
return mem[addr_to_index(raddr)];
}
/**
* Always writes to the 4 bytes at the address `waddr` & ~0x3u.
* Each bit in `wmask` represents a mask for one byte in wdata.
* For example, wmask = 0x3 means only the lowest 2 bytes are written,
* and the other bytes in memory remain unchanged.
*/
void write(int waddr, T wdata, char wmask) {
mem[addr_to_index((uint32_t)waddr)] = expand_bits(wmask) & wdata;
}
};
using VlModule = VlModuleInterfaceCommon<VFlow>;
using Registers = _RegistersVPI<uint32_t, 32>;
extern "C" {
void *pmem_get() {
static auto pmem = new Memory<int, 128 * 1024>;
void *pmem_get() {
static auto pmem = new Memory<int, 128 * 1024>(config.memory_file,
config.memory_file_binary);
return pmem;
}
int pmem_read(int raddr) {
void *pmem = pmem_get();
auto mem = static_cast<Memory<int, 128 * 1024>*>(pmem);
return mem->read(raddr);
}
void pmem_write(int waddr, int wdata, char wmask) {
void *pmem = pmem_get();
auto mem = static_cast<Memory<int, 128 * 1024>*>(pmem);
return mem->write((size_t)waddr, wdata, wmask);
}
}
template <typename T>
class VlModuleInterfaceCommon : public T {
uint64_t sim_time = 0;
uint64_t posedge_cnt = 0;
std::unique_ptr<Tracer<T>> tracer;
public:
VlModuleInterfaceCommon<T>(bool do_trace, std::filesystem::path wavefile = "waveform.vcd") {
if(do_trace) tracer = std::make_unique<Tracer<T>>(this, wavefile);
}
void eval() {
if(this->is_posedge()) {
posedge_cnt++;
}
T::clock = !T::clock;
sim_time++;
T::eval();
if(tracer) tracer->update();
}
void eval(int n) {
for(int i = 0; i < n; i++) {
this->eval();
}
}
void reset_eval(int n) {
this->reset = 1;
this->eval(n);
this->reset = 0;
}
bool is_posedge() {
// Will be posedge when eval is called
return T::clock == 0;
}
};
int pmem_read(int raddr) {
void *pmem = pmem_get();
auto mem = static_cast<Memory<int, 128 * 1024> *>(pmem);
return mem->read(raddr);
}
typedef VlModuleInterfaceCommon<VFlow> VlModule;
void pmem_write(int waddr, int wdata, char wmask) {
void *pmem = pmem_get();
auto mem = static_cast<Memory<int, 128 * 1024> *>(pmem);
return mem->write((std::size_t)waddr, wdata, wmask);
}
}
int main(int argc, char **argv, char **env) {
Verilated::commandArgs(argc, argv);
auto top = std::make_shared<VlModule>(false, "waveform.vcd");
config.cli_parse(argc, argv);
auto top = std::make_shared<VlModule>(config.do_trace, config.wavefile);
Registers regs("TOP.Flow.reg_0.regFile_");
top->reset_eval(10);
for (int i = 0; i < MAX_SIM_TIME; i++) {
if(top->is_posedge()) {
for (int i = 0; i < config.max_sim_time; i++) {
if (top->is_posedge()) {
// Posedge
regs.update();
regs.print_regs();

65
npc/csrc/Flow/vl_wrapper.hpp Normal file
View file

@ -0,0 +1,65 @@
#ifndef _NPC_TRACER_H_
#define _NPC_TRACER_H_
#include <filesystem>
#include <verilated_vcd_c.h>
template <class T> class Tracer {
std::shared_ptr<T> top;
std::unique_ptr<VerilatedVcdC> m_trace;
uint64_t cycle = 0;
public:
Tracer(T *top, std::filesystem::path wavefile) {
top = top;
Verilated::traceEverOn(true);
m_trace = std::make_unique<VerilatedVcdC>();
top->trace(m_trace.get(), 5);
m_trace->open(wavefile.c_str());
}
~Tracer() { m_trace->close(); }
/**
* Dump signals to waveform file. Must be called once after every top->eval()
* call.
*/
void update() { m_trace->dump(cycle++); }
};
template <typename T> class VlModuleInterfaceCommon : public T {
uint64_t sim_time = 0;
uint64_t posedge_cnt = 0;
std::unique_ptr<Tracer<T>> tracer;
public:
VlModuleInterfaceCommon<T>(bool do_trace,
std::filesystem::path wavefile = "waveform.vcd") {
if (do_trace)
tracer = std::make_unique<Tracer<T>>(this, wavefile);
}
void eval() {
if (this->is_posedge()) {
posedge_cnt++;
}
T::clock = !T::clock;
sim_time++;
T::eval();
if (tracer)
tracer->update();
}
void eval(int n) {
for (int i = 0; i < n; i++) {
this->eval();
}
}
void reset_eval(int n) {
this->reset = 1;
this->eval(n);
this->reset = 0;
}
bool is_posedge() {
// Will be posedge when eval is called
return T::clock == 0;
}
};
#endif

113
npc/flake.lock
View file

@ -1,5 +1,21 @@
{
"nodes": {
"flake-compat": {
"flake": false,
"locked": {
"lastModified": 1696426674,
"narHash": "sha256-kvjfFW7WAETZlt09AgDn1MrtKzP7t90Vf7vypd3OL1U=",
"owner": "edolstra",
"repo": "flake-compat",
"rev": "0f9255e01c2351cc7d116c072cb317785dd33b33",
"type": "github"
},
"original": {
"owner": "edolstra",
"repo": "flake-compat",
"type": "github"
}
},
"flake-utils": {
"inputs": {
"systems": "systems"
@ -18,6 +34,45 @@
"type": "github"
}
},
"flake-utils_2": {
"inputs": {
"systems": "systems_2"
},
"locked": {
"lastModified": 1710146030,
"narHash": "sha256-SZ5L6eA7HJ/nmkzGG7/ISclqe6oZdOZTNoesiInkXPQ=",
"owner": "numtide",
"repo": "flake-utils",
"rev": "b1d9ab70662946ef0850d488da1c9019f3a9752a",
"type": "github"
},
"original": {
"owner": "numtide",
"repo": "flake-utils",
"type": "github"
}
},
"gitignore": {
"inputs": {
"nixpkgs": [
"pre-commit-hooks",
"nixpkgs"
]
},
"locked": {
"lastModified": 1709087332,
"narHash": "sha256-HG2cCnktfHsKV0s4XW83gU3F57gaTljL9KNSuG6bnQs=",
"owner": "hercules-ci",
"repo": "gitignore.nix",
"rev": "637db329424fd7e46cf4185293b9cc8c88c95394",
"type": "github"
},
"original": {
"owner": "hercules-ci",
"repo": "gitignore.nix",
"type": "github"
}
},
"nixpkgs": {
"locked": {
"lastModified": 1709961763,
@ -50,6 +105,22 @@
"type": "github"
}
},
"nixpkgs-stable": {
"locked": {
"lastModified": 1710695816,
"narHash": "sha256-3Eh7fhEID17pv9ZxrPwCLfqXnYP006RKzSs0JptsN84=",
"owner": "NixOS",
"repo": "nixpkgs",
"rev": "614b4613980a522ba49f0d194531beddbb7220d3",
"type": "github"
},
"original": {
"owner": "NixOS",
"ref": "nixos-23.11",
"repo": "nixpkgs",
"type": "github"
}
},
"nur-xin": {
"inputs": {
"nixpkgs": [
@ -70,12 +141,37 @@
"url": "https://git.xinyang.life/xin/nur.git"
}
},
"pre-commit-hooks": {
"inputs": {
"flake-compat": "flake-compat",
"flake-utils": "flake-utils_2",
"gitignore": "gitignore",
"nixpkgs": [
"nixpkgs"
],
"nixpkgs-stable": "nixpkgs-stable"
},
"locked": {
"lastModified": 1712055707,
"narHash": "sha256-4XLvuSIDZJGS17xEwSrNuJLL7UjDYKGJSbK1WWX2AK8=",
"owner": "cachix",
"repo": "pre-commit-hooks.nix",
"rev": "e35aed5fda3cc79f88ed7f1795021e559582093a",
"type": "github"
},
"original": {
"owner": "cachix",
"repo": "pre-commit-hooks.nix",
"type": "github"
}
},
"root": {
"inputs": {
"flake-utils": "flake-utils",
"nixpkgs": "nixpkgs",
"nixpkgs-circt162": "nixpkgs-circt162",
"nur-xin": "nur-xin"
"nur-xin": "nur-xin",
"pre-commit-hooks": "pre-commit-hooks"
}
},
"systems": {
@ -92,6 +188,21 @@
"repo": "default",
"type": "github"
}
},
"systems_2": {
"locked": {
"lastModified": 1681028828,
"narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=",
"owner": "nix-systems",
"repo": "default",
"rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e",
"type": "github"
},
"original": {
"owner": "nix-systems",
"repo": "default",
"type": "github"
}
}
},
"root": "root",

19
npc/flake.nix
View file

@ -3,6 +3,10 @@
nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
nixpkgs-circt162.url = "github:NixOS/nixpkgs/7995cae3ad60e3d6931283d650d7f43d31aaa5c7";
flake-utils.url = "github:numtide/flake-utils";
pre-commit-hooks = {
url = "github:cachix/pre-commit-hooks.nix";
inputs.nixpkgs.follows = "nixpkgs";
};
nur-xin = {
url = "git+https://git.xinyang.life/xin/nur.git";
inputs.nixpkgs.follows = "nixpkgs";
@ -16,7 +20,21 @@
{ nur.xin = nur-xin.legacyPackages.${system}; };
in
{
checks = {
pre-commit-check = pre-commit-hooks.lib.${system}.run {
src = ./.;
hooks = {
trim-trailing-whitespace.enable = true;
clang-format = {
enable = true;
types_or = pkgs.lib.mkForce [ "c" "c++" ];
};
};
};
};
devShells.default = with pkgs; mkShell {
inherit (self.checks.${system}.pre-commit-check) shellHook;
buildInputs = self.checks.${system}.pre-commit-check.enabledPackages;
CHISEL_FIRTOOL_PATH = "${nixpkgs-circt162.legacyPackages.${system}.circt}/bin";
packages = [
clang-tools
@ -43,6 +61,7 @@
nur.xin.nvboard
nixpkgs-circt162.legacyPackages.${system}.circt
yosys
cli11
];
buildInputs = [
verilator