nemu,chore: reformat c/c++ code
This commit is contained in:
parent
a5790308f0
commit
96ae890632
8 changed files with 84 additions and 96 deletions
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@ -1,5 +1,4 @@
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menuconfig DEVICE
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menuconfig DEVICE
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depends on !TARGET_SHARE
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bool "Devices"
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bool "Devices"
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default n
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default n
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help
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help
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@ -13,17 +13,17 @@
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* See the Mulan PSL v2 for more details.
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* See the Mulan PSL v2 for more details.
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***************************************************************************************/
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***************************************************************************************/
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#include <device/map.h>
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#include <isa.h>
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#include <isa.h>
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#include <memory/host.h>
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#include <memory/host.h>
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#include <memory/vaddr.h>
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#include <memory/vaddr.h>
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#include <device/map.h>
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#define IO_SPACE_MAX (2 * 1024 * 1024)
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#define IO_SPACE_MAX (2 * 1024 * 1024)
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static uint8_t *io_space = NULL;
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static uint8_t *io_space = NULL;
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static uint8_t *p_space = NULL;
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static uint8_t *p_space = NULL;
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uint8_t* new_space(int size) {
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uint8_t *new_space(int size) {
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uint8_t *p = p_space;
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uint8_t *p = p_space;
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// page aligned;
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// page aligned;
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size = (size + (PAGE_SIZE - 1)) & ~PAGE_MASK;
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size = (size + (PAGE_SIZE - 1)) & ~PAGE_MASK;
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@ -33,17 +33,25 @@ uint8_t* new_space(int size) {
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}
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}
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static void check_bound(IOMap *map, paddr_t addr) {
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static void check_bound(IOMap *map, paddr_t addr) {
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#ifndef CONFIG_TARGET_SHARE
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if (map == NULL) {
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if (map == NULL) {
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Assert(map != NULL, "address (" FMT_PADDR ") is out of bound at pc = " FMT_WORD, addr, cpu.pc);
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Assert(map != NULL,
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"address (" FMT_PADDR ") is out of bound at pc = " FMT_WORD, addr,
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cpu.pc);
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} else {
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} else {
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Assert(addr <= map->high && addr >= map->low,
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Assert(addr <= map->high && addr >= map->low,
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"address (" FMT_PADDR ") is out of bound {%s} [" FMT_PADDR ", " FMT_PADDR "] at pc = " FMT_WORD,
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"address (" FMT_PADDR ") is out of bound {%s} [" FMT_PADDR
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addr, map->name, map->low, map->high, cpu.pc);
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", " FMT_PADDR "] at pc = " FMT_WORD,
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addr, map->name, map->low, map->high, cpu.pc);
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}
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}
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#endif
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}
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}
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static void invoke_callback(io_callback_t c, paddr_t offset, int len, bool is_write) {
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static void invoke_callback(io_callback_t c, paddr_t offset, int len,
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if (c != NULL) { c(offset, len, is_write); }
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bool is_write) {
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if (c != NULL) {
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c(offset, len, is_write);
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}
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}
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}
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void init_map() {
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void init_map() {
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@ -86,38 +86,16 @@ static void decode_operand(Decode *s, int *rd, word_t *src1, word_t *src2,
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int rs2 = BITS(i, 24, 20);
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int rs2 = BITS(i, 24, 20);
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*rd = BITS(i, 11, 7);
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*rd = BITS(i, 11, 7);
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switch (type) {
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switch (type) {
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case TYPE_R:
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// clang-format off
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src1R();
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case TYPE_R: src1R(); src2R(); break;
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src2R();
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case TYPE_I: src1R(); immI(); break;
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break;
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case TYPE_U: immU(); break;
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case TYPE_I:
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case TYPE_J: immJ(); break;
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src1R();
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case TYPE_S: src1R(); src2R(); immS(); break;
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immI();
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case TYPE_B: src1R(); src2R(); immB(); break;
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break;
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case TYPE_CSR: src1R(); csr(); break;
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case TYPE_U:
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case TYPE_CSRI: csr(); uimm(); break;
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immU();
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// clang-format on
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break;
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case TYPE_J:
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immJ();
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break;
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case TYPE_S:
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src1R();
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src2R();
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immS();
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break;
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case TYPE_B:
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src1R();
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src2R();
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immB();
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break;
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case TYPE_CSR:
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src1R();
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csr();
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break;
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case TYPE_CSRI:
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csr();
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uimm();
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break;
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}
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}
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}
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}
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@ -271,6 +249,9 @@ static int decode_exec(Decode *s) {
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// "Previledge"
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// "Previledge"
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// -- CSR instructions
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// -- CSR instructions
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// src2: R(read register)
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// src1: R(write source)
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// imm: write data()
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INSTPAT(
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INSTPAT(
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"??????? ????? ????? 001 ????? 11100 11", csrrw, CSR, do {
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"??????? ????? ????? 001 ????? 11100 11", csrrw, CSR, do {
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R(rd) = read_csr(cpu.csr, src2);
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R(rd) = read_csr(cpu.csr, src2);
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@ -52,13 +52,11 @@ word_t isa_reg_str2val(const char *s, bool *success) {
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}
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}
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int isa_read_reg(void *args, int regno, size_t *reg_value) {
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int isa_read_reg(void *args, int regno, size_t *reg_value) {
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if (regno > 33) {
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if (regno > 32) {
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return EFAULT;
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return EFAULT;
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}
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}
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if (regno == 33) {
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if (regno == 32) {
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*reg_value = cpu.csr[MTVEC];
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} else if (regno == 32) {
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*reg_value = cpu.pc;
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*reg_value = cpu.pc;
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} else {
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} else {
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*reg_value = cpu.gpr[regno];
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*reg_value = cpu.gpr[regno];
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@ -67,13 +65,11 @@ int isa_read_reg(void *args, int regno, size_t *reg_value) {
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}
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}
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int isa_write_reg(void *args, int regno, size_t data) {
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int isa_write_reg(void *args, int regno, size_t data) {
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if (regno > 33) {
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if (regno > 32) {
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return EFAULT;
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return EFAULT;
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}
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}
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if (regno == 33) {
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if (regno == 32) {
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cpu.csr[MTVEC] = data;
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} else if (regno == 32) {
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cpu.pc = data;
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cpu.pc = data;
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} else {
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} else {
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cpu.gpr[regno] = data;
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cpu.gpr[regno] = data;
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@ -81,6 +77,6 @@ int isa_write_reg(void *args, int regno, size_t data) {
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return 0;
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return 0;
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}
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}
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__EXPORT arch_info_t isa_arch_info = {.reg_num = 33,
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__EXPORT arch_info_t isa_arch_info = {.reg_num = 32,
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.reg_byte = MUXDEF(CONFIG_RV64, 8, 4),
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.reg_byte = MUXDEF(CONFIG_RV64, 8, 4),
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.target_desc = TARGET_RV32};
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.target_desc = TARGET_RV32};
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@ -15,6 +15,7 @@
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#include "common.h"
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#include "common.h"
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#include "debug.h"
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#include "debug.h"
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#include "utils.h"
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#include <device/mmio.h>
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#include <device/mmio.h>
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#include <isa.h>
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#include <isa.h>
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#include <memory/host.h>
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#include <memory/host.h>
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@ -44,9 +45,14 @@ static void pmem_write(paddr_t addr, int len, word_t data) {
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}
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}
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static void out_of_bound(paddr_t addr) {
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static void out_of_bound(paddr_t addr) {
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#ifdef CONFIG_TARGET_SHARE
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// Do not panic when used as a library. Give an error in log
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Error("Out of bound at 0x%x", addr);
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#else
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panic("address = " FMT_PADDR " is out of bound of pmem [" FMT_PADDR
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panic("address = " FMT_PADDR " is out of bound of pmem [" FMT_PADDR
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", " FMT_PADDR "] at pc = " FMT_WORD,
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", " FMT_PADDR "] at pc = " FMT_WORD,
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addr, PMEM_LEFT, PMEM_RIGHT, cpu.pc);
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addr, PMEM_LEFT, PMEM_RIGHT, cpu.pc);
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#endif
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}
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}
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#ifdef CONFIG_MTRACE
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#ifdef CONFIG_MTRACE
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#include "types.h"
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#include "utils.h"
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#include "utils.h"
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#include <vector>
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#include <vector>
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__EXPORT size_t nemu_dbg_state_size = sizeof(DbgState);
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__EXPORT size_t nemu_dbg_state_size = sizeof(DbgState);
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__EXPORT bool nemu_do_difftest = true;
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__EXPORT bool nemu_do_difftest = true;
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__EXPORT arch_info_t nemu_isa_arch_info;
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__EXPORT arch_info_t nemu_isa_arch_info = isa_arch_info;
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__EXPORT int nemu_read_mem(void *args, size_t addr, size_t len, void *val) {
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__EXPORT int nemu_read_mem(void *args, size_t addr, size_t len, void *val) {
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if (!in_pmem(addr))
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if (!in_pmem(addr))
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@ -59,7 +59,8 @@ extern "C" void init_disasm(const char *triple) {
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llvm::MCRegisterInfo *gMRI = nullptr;
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llvm::MCRegisterInfo *gMRI = nullptr;
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auto target = llvm::TargetRegistry::lookupTarget(gTriple, errstr);
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auto target = llvm::TargetRegistry::lookupTarget(gTriple, errstr);
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if (!target) {
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if (!target) {
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llvm::errs() << "Can't find target for " << gTriple << ": " << errstr << "\n";
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llvm::errs() << "Can't find target for " << gTriple << ": " << errstr
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<< "\n";
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assert(0);
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assert(0);
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}
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}
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@ -77,22 +78,24 @@ extern "C" void init_disasm(const char *triple) {
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gMRI = target->createMCRegInfo(gTriple);
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gMRI = target->createMCRegInfo(gTriple);
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auto AsmInfo = target->createMCAsmInfo(*gMRI, gTriple, MCOptions);
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auto AsmInfo = target->createMCAsmInfo(*gMRI, gTriple, MCOptions);
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#if LLVM_VERSION_MAJOR >= 13
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#if LLVM_VERSION_MAJOR >= 13
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auto llvmTripleTwine = Twine(triple);
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auto llvmTripleTwine = Twine(triple);
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auto llvmtriple = llvm::Triple(llvmTripleTwine);
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auto llvmtriple = llvm::Triple(llvmTripleTwine);
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auto Ctx = new llvm::MCContext(llvmtriple,AsmInfo, gMRI, nullptr);
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auto Ctx = new llvm::MCContext(llvmtriple, AsmInfo, gMRI, nullptr);
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#else
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#else
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auto Ctx = new llvm::MCContext(AsmInfo, gMRI, nullptr);
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auto Ctx = new llvm::MCContext(AsmInfo, gMRI, nullptr);
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#endif
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#endif
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gDisassembler = target->createMCDisassembler(*gSTI, *Ctx);
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gDisassembler = target->createMCDisassembler(*gSTI, *Ctx);
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gIP = target->createMCInstPrinter(llvm::Triple(gTriple),
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gIP = target->createMCInstPrinter(llvm::Triple(gTriple),
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AsmInfo->getAssemblerDialect(), *AsmInfo, *gMII, *gMRI);
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AsmInfo->getAssemblerDialect(), *AsmInfo,
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*gMII, *gMRI);
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gIP->setPrintImmHex(true);
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gIP->setPrintImmHex(true);
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gIP->setPrintBranchImmAsAddress(true);
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gIP->setPrintBranchImmAsAddress(true);
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if (isa == "riscv32" || isa == "riscv64")
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if (isa == "riscv32" || isa == "riscv64")
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gIP->applyTargetSpecificCLOption("no-aliases");
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gIP->applyTargetSpecificCLOption("no-aliases");
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}
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}
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extern "C" void disassemble(char *str, int size, uint64_t pc, uint8_t *code, int nbyte) {
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extern "C" void disassemble(char *str, int size, uint64_t pc, uint8_t *code,
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int nbyte) {
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MCInst inst;
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MCInst inst;
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llvm::ArrayRef<uint8_t> arr(code, nbyte);
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llvm::ArrayRef<uint8_t> arr(code, nbyte);
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uint64_t dummy_size = 0;
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uint64_t dummy_size = 0;
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* See the Mulan PSL v2 for more details.
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* See the Mulan PSL v2 for more details.
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***************************************************************************************/
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***************************************************************************************/
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#include "../../include/common.h"
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#include "mmu.h"
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#include "mmu.h"
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#include "sim.h"
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#include "sim.h"
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#include "../../include/common.h"
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#include <difftest-def.h>
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#include <difftest-def.h>
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#define NR_GPR MUXDEF(CONFIG_RVE, 16, 32)
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#define NR_GPR MUXDEF(CONFIG_RVE, 16, 32)
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static std::vector<std::pair<reg_t, abstract_device_t*>> difftest_plugin_devices;
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static std::vector<std::pair<reg_t, abstract_device_t *>>
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difftest_plugin_devices;
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static std::vector<std::string> difftest_htif_args;
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static std::vector<std::string> difftest_htif_args;
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static std::vector<std::pair<reg_t, mem_t*>> difftest_mem(
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static std::vector<std::pair<reg_t, mem_t *>>
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1, std::make_pair(reg_t(DRAM_BASE), new mem_t(CONFIG_MSIZE)));
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difftest_mem(1, std::make_pair(reg_t(DRAM_BASE), new mem_t(CONFIG_MSIZE)));
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static debug_module_config_t difftest_dm_config = {
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static debug_module_config_t difftest_dm_config = {
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.progbufsize = 2,
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.progbufsize = 2,
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.max_sba_data_width = 0,
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.max_sba_data_width = 0,
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.require_authentication = false,
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.require_authentication = false,
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.abstract_rti = 0,
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.abstract_rti = 0,
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.support_hasel = true,
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.support_hasel = true,
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.support_abstract_csr_access = true,
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.support_abstract_csr_access = true,
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.support_abstract_fpr_access = true,
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.support_abstract_fpr_access = true,
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.support_haltgroups = true,
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.support_haltgroups = true,
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.support_impebreak = true
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.support_impebreak = true};
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};
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struct diff_context_t {
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struct diff_context_t {
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word_t gpr[MUXDEF(CONFIG_RVE, 16, 32)];
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word_t gpr[MUXDEF(CONFIG_RVE, 16, 32)];
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word_t pc;
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word_t pc;
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};
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};
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static sim_t* s = NULL;
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static sim_t *s = NULL;
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static processor_t *p = NULL;
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static processor_t *p = NULL;
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static state_t *state = NULL;
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static state_t *state = NULL;
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@ -50,36 +50,35 @@ void sim_t::diff_init(int port) {
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state = p->get_state();
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state = p->get_state();
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}
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}
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void sim_t::diff_step(uint64_t n) {
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void sim_t::diff_step(uint64_t n) { step(n); }
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step(n);
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}
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void sim_t::diff_get_regs(void* diff_context) {
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void sim_t::diff_get_regs(void *diff_context) {
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struct diff_context_t* ctx = (struct diff_context_t*)diff_context;
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struct diff_context_t *ctx = (struct diff_context_t *)diff_context;
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for (int i = 0; i < NR_GPR; i++) {
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for (int i = 0; i < NR_GPR; i++) {
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ctx->gpr[i] = state->XPR[i];
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ctx->gpr[i] = state->XPR[i];
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}
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}
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ctx->pc = state->pc;
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ctx->pc = state->pc;
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}
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}
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void sim_t::diff_set_regs(void* diff_context) {
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void sim_t::diff_set_regs(void *diff_context) {
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struct diff_context_t* ctx = (struct diff_context_t*)diff_context;
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struct diff_context_t *ctx = (struct diff_context_t *)diff_context;
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for (int i = 0; i < NR_GPR; i++) {
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for (int i = 0; i < NR_GPR; i++) {
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state->XPR.write(i, (sword_t)ctx->gpr[i]);
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state->XPR.write(i, (sword_t)ctx->gpr[i]);
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}
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}
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state->pc = ctx->pc;
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state->pc = ctx->pc;
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}
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}
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void sim_t::diff_memcpy(reg_t dest, void* src, size_t n) {
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void sim_t::diff_memcpy(reg_t dest, void *src, size_t n) {
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mmu_t* mmu = p->get_mmu();
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mmu_t *mmu = p->get_mmu();
|
||||||
for (size_t i = 0; i < n; i++) {
|
for (size_t i = 0; i < n; i++) {
|
||||||
mmu->store<uint8_t>(dest+i, *((uint8_t*)src+i));
|
mmu->store<uint8_t>(dest + i, *((uint8_t *)src + i));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
extern "C" {
|
extern "C" {
|
||||||
|
|
||||||
__EXPORT void difftest_memcpy(paddr_t addr, void *buf, size_t n, bool direction) {
|
__EXPORT void difftest_memcpy(paddr_t addr, void *buf, size_t n,
|
||||||
|
bool direction) {
|
||||||
if (direction == DIFFTEST_TO_REF) {
|
if (direction == DIFFTEST_TO_REF) {
|
||||||
s->diff_memcpy(addr, buf, n);
|
s->diff_memcpy(addr, buf, n);
|
||||||
} else {
|
} else {
|
||||||
|
@ -87,7 +86,7 @@ __EXPORT void difftest_memcpy(paddr_t addr, void *buf, size_t n, bool direction)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
__EXPORT void difftest_regcpy(void* dut, bool direction) {
|
__EXPORT void difftest_regcpy(void *dut, bool direction) {
|
||||||
if (direction == DIFFTEST_TO_REF) {
|
if (direction == DIFFTEST_TO_REF) {
|
||||||
s->diff_set_regs(dut);
|
s->diff_set_regs(dut);
|
||||||
} else {
|
} else {
|
||||||
|
@ -95,31 +94,27 @@ __EXPORT void difftest_regcpy(void* dut, bool direction) {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
__EXPORT void difftest_exec(uint64_t n) {
|
__EXPORT void difftest_exec(uint64_t n) { s->diff_step(n); }
|
||||||
s->diff_step(n);
|
|
||||||
}
|
|
||||||
|
|
||||||
__EXPORT void difftest_init(int port) {
|
__EXPORT void difftest_init(int port) {
|
||||||
difftest_htif_args.push_back("");
|
difftest_htif_args.push_back("");
|
||||||
const char *isa = "RV" MUXDEF(CONFIG_RV64, "64", "32") MUXDEF(CONFIG_RVE, "E", "I") "MAFDC";
|
const char *isa =
|
||||||
|
"RV" MUXDEF(CONFIG_RV64, "64", "32") MUXDEF(CONFIG_RVE, "E", "I") "MAFDC";
|
||||||
cfg_t cfg(/*default_initrd_bounds=*/std::make_pair((reg_t)0, (reg_t)0),
|
cfg_t cfg(/*default_initrd_bounds=*/std::make_pair((reg_t)0, (reg_t)0),
|
||||||
/*default_bootargs=*/nullptr,
|
/*default_bootargs=*/nullptr,
|
||||||
/*default_isa=*/isa,
|
/*default_isa=*/isa,
|
||||||
/*default_priv=*/DEFAULT_PRIV,
|
/*default_priv=*/DEFAULT_PRIV,
|
||||||
/*default_varch=*/DEFAULT_VARCH,
|
/*default_varch=*/DEFAULT_VARCH,
|
||||||
/*default_misaligned=*/false,
|
/*default_misaligned=*/false,
|
||||||
/*default_endianness*/endianness_little,
|
/*default_endianness*/ endianness_little,
|
||||||
/*default_pmpregions=*/16,
|
/*default_pmpregions=*/16,
|
||||||
/*default_mem_layout=*/std::vector<mem_cfg_t>(),
|
/*default_mem_layout=*/std::vector<mem_cfg_t>(),
|
||||||
/*default_hartids=*/std::vector<size_t>(1),
|
/*default_hartids=*/std::vector<size_t>(1),
|
||||||
/*default_real_time_clint=*/false,
|
/*default_real_time_clint=*/false,
|
||||||
/*default_trigger_count=*/4);
|
/*default_trigger_count=*/4);
|
||||||
s = new sim_t(&cfg, false,
|
s = new sim_t(&cfg, false, difftest_mem, difftest_plugin_devices,
|
||||||
difftest_mem, difftest_plugin_devices, difftest_htif_args,
|
difftest_htif_args, difftest_dm_config, nullptr, false, NULL,
|
||||||
difftest_dm_config, nullptr, false, NULL,
|
false, NULL, true);
|
||||||
false,
|
|
||||||
NULL,
|
|
||||||
true);
|
|
||||||
s->diff_init(port);
|
s->diff_init(port);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -127,5 +122,4 @@ __EXPORT void difftest_raise_intr(uint64_t NO) {
|
||||||
trap_t t(NO);
|
trap_t t(NO);
|
||||||
p->take_trap_public(t, state->pc);
|
p->take_trap_public(t, state->pc);
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue