nemu: support yield()
This commit is contained in:
parent
ef51673020
commit
961ba84a54
19 changed files with 223 additions and 81 deletions
2
.gitmodules
vendored
2
.gitmodules
vendored
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@ -4,4 +4,4 @@
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branch = dev
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branch = dev
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[submodule "diffu"]
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[submodule "diffu"]
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path = diffu
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path = diffu
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url = https://git.xinyang.life/xin/diffu.git
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url = git@github.com:xinyangli/diffu.git
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@ -76,7 +76,8 @@ target_include_directories(
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INTERFACE $<BUILD_INTERFACE:${CMAKE_SOURCE_DIR}/am/include>
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INTERFACE $<BUILD_INTERFACE:${CMAKE_SOURCE_DIR}/am/include>
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$<BUILD_INTERFACE:${CMAKE_SOURCE_DIR}/am/src>
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$<BUILD_INTERFACE:${CMAKE_SOURCE_DIR}/am/src>
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$<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>)
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$<INSTALL_INTERFACE:${CMAKE_INSTALL_INCLUDEDIR}>)
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target_compile_definitions(am_interface INTERFACE ARCH_H=<arch/${ISA}.h>)
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target_compile_definitions(am_interface INTERFACE ARCH_H=<arch/${ISA}.h>
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"__ISA__=\"${ISA}\"")
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file(GLOB_RECURSE AM_HEADERS "${CMAKE_SOURCE_DIR}/am/include/*.h")
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file(GLOB_RECURSE AM_HEADERS "${CMAKE_SOURCE_DIR}/am/include/*.h")
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target_sources(
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target_sources(
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am_interface
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am_interface
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@ -1,5 +1,6 @@
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#ifndef ARCH_H__
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#ifndef ARCH_H__
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#define ARCH_H__
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#define ARCH_H__
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#include <stdint.h>
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#ifdef __riscv_e
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#ifdef __riscv_e
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#define NR_REGS 16
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#define NR_REGS 16
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@ -9,10 +10,13 @@
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struct Context {
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struct Context {
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// TODO: fix the order of these members to match trap.S
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// TODO: fix the order of these members to match trap.S
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uintptr_t mepc, mcause, gpr[NR_REGS], mstatus;
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uintptr_t gpr[NR_REGS];
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uintptr_t mcause, mstatus, mepc;
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void *pdir;
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void *pdir;
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};
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};
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enum Cause { CauseEnvironmentCallFromMMode = 11 };
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#ifdef __riscv_e
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#ifdef __riscv_e
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#define GPR1 gpr[15] // a5
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#define GPR1 gpr[15] // a5
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#else
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#else
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@ -6,7 +6,7 @@ int main(const char *args);
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Area heap = RANGE(&_heap_start, PMEM_END);
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Area heap = RANGE(&_heap_start, PMEM_END);
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#ifndef MAINARGS
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#ifndef MAINARGS
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#define MAINARGS "5"
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#define MAINARGS "i"
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#endif
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#endif
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static const char mainargs[] = MAINARGS;
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static const char mainargs[] = MAINARGS;
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@ -1,14 +1,20 @@
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#include "arch/riscv.h"
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#include <am.h>
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#include <am.h>
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#include <riscv/riscv.h>
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#include <klib.h>
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#include <klib.h>
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#include <riscv/riscv.h>
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static Context* (*user_handler)(Event, Context*) = NULL;
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static Context *(*user_handler)(Event, Context *) = NULL;
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Context* __am_irq_handle(Context *c) {
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Context *__am_irq_handle(Context *c) {
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if (user_handler) {
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if (user_handler) {
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Event ev = {0};
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Event ev = {0};
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switch (c->mcause) {
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switch (c->mcause) {
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default: ev.event = EVENT_ERROR; break;
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case CauseEnvironmentCallFromMMode:
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ev.event = EVENT_YIELD;
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break;
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default:
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ev.event = EVENT_ERROR;
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break;
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}
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}
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c = user_handler(ev, c);
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c = user_handler(ev, c);
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@ -20,7 +26,7 @@ Context* __am_irq_handle(Context *c) {
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extern void __am_asm_trap(void);
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extern void __am_asm_trap(void);
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bool cte_init(Context*(*handler)(Event, Context*)) {
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bool cte_init(Context *(*handler)(Event, Context *)) {
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// initialize exception entry
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// initialize exception entry
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asm volatile("csrw mtvec, %0" : : "r"(__am_asm_trap));
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asm volatile("csrw mtvec, %0" : : "r"(__am_asm_trap));
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@ -42,9 +48,6 @@ void yield() {
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#endif
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#endif
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}
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}
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bool ienabled() {
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bool ienabled() { return false; }
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return false;
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}
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void iset(bool enable) {
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void iset(bool enable) {}
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}
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@ -15,6 +15,9 @@ stdenv.mkDerivation {
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(lib.cmakeFeature "ISA" isa)
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(lib.cmakeFeature "ISA" isa)
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] ++ map (p: (lib.cmakeBool "__PLATFORM_${lib.strings.toUpper p}__" true)) platform;
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] ++ map (p: (lib.cmakeBool "__PLATFORM_${lib.strings.toUpper p}__" true)) platform;
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cmakeBuildType = "Debug";
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dontStrip = true;
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nativeBuildInputs = [
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nativeBuildInputs = [
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cmake
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cmake
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];
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];
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@ -1 +1 @@
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Subproject commit 02b38e7b44f673f808abcb3bf9464811f8c58d4b
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Subproject commit 8c4ea046225e2dce599dc36aeef6c4c857996d00
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1
nemu/.gitignore
vendored
1
nemu/.gitignore
vendored
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@ -9,6 +9,7 @@ build/
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.envrc
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.envrc
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.metals/
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.metals/
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.vscode/
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.vscode/
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.zed/
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compile_commands.json
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compile_commands.json
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### C ###
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### C ###
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@ -20,7 +20,14 @@
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// ----------- state -----------
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// ----------- state -----------
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enum { NEMU_RUNNING, NEMU_STOP, NEMU_END, NEMU_ABORT, NEMU_QUIT };
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enum {
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NEMU_RUNNING,
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NEMU_GDB_INTERRUPT,
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NEMU_STOP,
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NEMU_END,
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NEMU_ABORT,
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NEMU_QUIT
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};
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typedef struct {
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typedef struct {
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int state;
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int state;
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@ -36,42 +43,41 @@ uint64_t get_time();
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// ----------- log -----------
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// ----------- log -----------
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#define ANSI_FG_BLACK "\33[1;30m"
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#define ANSI_FG_BLACK "\33[1;30m"
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#define ANSI_FG_RED "\33[1;31m"
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#define ANSI_FG_RED "\33[1;31m"
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#define ANSI_FG_GREEN "\33[1;32m"
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#define ANSI_FG_GREEN "\33[1;32m"
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#define ANSI_FG_YELLOW "\33[1;33m"
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#define ANSI_FG_YELLOW "\33[1;33m"
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#define ANSI_FG_BLUE "\33[1;34m"
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#define ANSI_FG_BLUE "\33[1;34m"
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#define ANSI_FG_MAGENTA "\33[1;35m"
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#define ANSI_FG_MAGENTA "\33[1;35m"
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#define ANSI_FG_CYAN "\33[1;36m"
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#define ANSI_FG_CYAN "\33[1;36m"
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#define ANSI_FG_WHITE "\33[1;37m"
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#define ANSI_FG_WHITE "\33[1;37m"
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#define ANSI_BG_BLACK "\33[1;40m"
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#define ANSI_BG_BLACK "\33[1;40m"
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#define ANSI_BG_RED "\33[1;41m"
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#define ANSI_BG_RED "\33[1;41m"
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#define ANSI_BG_GREEN "\33[1;42m"
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#define ANSI_BG_GREEN "\33[1;42m"
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#define ANSI_BG_YELLOW "\33[1;43m"
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#define ANSI_BG_YELLOW "\33[1;43m"
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#define ANSI_BG_BLUE "\33[1;44m"
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#define ANSI_BG_BLUE "\33[1;44m"
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#define ANSI_BG_MAGENTA "\33[1;35m"
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#define ANSI_BG_MAGENTA "\33[1;35m"
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#define ANSI_BG_CYAN "\33[1;46m"
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#define ANSI_BG_CYAN "\33[1;46m"
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#define ANSI_BG_WHITE "\33[1;47m"
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#define ANSI_BG_WHITE "\33[1;47m"
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#define ANSI_NONE "\33[0m"
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#define ANSI_NONE "\33[0m"
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#define ANSI_FMT(str, fmt) fmt str ANSI_NONE
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#define ANSI_FMT(str, fmt) fmt str ANSI_NONE
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#define log_write(...) IFDEF(CONFIG_TARGET_NATIVE_ELF, \
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#define log_write(...) \
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do { \
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IFDEF( \
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extern FILE* log_fp; \
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CONFIG_TARGET_NATIVE_ELF, do { \
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extern bool log_enable(); \
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extern FILE *log_fp; \
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if (log_enable()) { \
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extern bool log_enable(); \
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fprintf(log_fp, __VA_ARGS__); \
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if (log_enable()) { \
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fflush(log_fp); \
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fprintf(log_fp, __VA_ARGS__); \
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} \
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fflush(log_fp); \
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} while (0) \
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} \
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)
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} while (0))
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#define _Log(...) \
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#define _Log(...) \
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do { \
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do { \
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printf(__VA_ARGS__); \
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printf(__VA_ARGS__); \
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log_write(__VA_ARGS__); \
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log_write(__VA_ARGS__); \
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} while (0)
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} while (0)
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#endif
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#endif
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* See the Mulan PSL v2 for more details.
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* See the Mulan PSL v2 for more details.
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***************************************************************************************/
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***************************************************************************************/
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#include <assert.h>
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#include <debug.h>
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#include <device/map.h>
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#include <device/map.h>
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#include <generated/autoconf.h>
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#include <utils.h>
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#include <utils.h>
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#define KEYDOWN_MASK 0x8000
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#define KEYDOWN_MASK 0x8000
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#include <SDL2/SDL.h>
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#include <SDL2/SDL.h>
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// Note that this is not the standard
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// Note that this is not the standard
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#define NEMU_KEYS(f) \
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#define NEMU_KEYS(f) \
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f(ESCAPE) f(F1) f(F2) f(F3) f(F4) f(F5) f(F6) f(F7) f(F8) f(F9) f(F10) f(F11) f(F12) \
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f(ESCAPE) f(F1) f(F2) f(F3) f(F4) f(F5) f(F6) f(F7) f(F8) f(F9) f(F10) \
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f(GRAVE) f(1) f(2) f(3) f(4) f(5) f(6) f(7) f(8) f(9) f(0) f(MINUS) f(EQUALS) f(BACKSPACE) \
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f(F11) f(F12) f(GRAVE) f(1) f(2) f(3) f(4) f(5) f(6) f(7) f(8) f(9) f(0) \
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f(TAB) f(Q) f(W) f(E) f(R) f(T) f(Y) f(U) f(I) f(O) f(P) f(LEFTBRACKET) f(RIGHTBRACKET) f(BACKSLASH) \
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f(MINUS) f(EQUALS) f(BACKSPACE) f(TAB) f(Q) f(W) f(E) f(R) f(T) f(Y) \
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f(CAPSLOCK) f(A) f(S) f(D) f(F) f(G) f(H) f(J) f(K) f(L) f(SEMICOLON) f(APOSTROPHE) f(RETURN) \
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f(U) f(I) f(O) f(P) f(LEFTBRACKET) f(RIGHTBRACKET) f(BACKSLASH) \
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f(LSHIFT) f(Z) f(X) f(C) f(V) f(B) f(N) f(M) f(COMMA) f(PERIOD) f(SLASH) f(RSHIFT) \
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f(CAPSLOCK) f(A) f(S) f(D) f(F) f(G) f(H) f(J) f(K) f(L) \
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f(LCTRL) f(APPLICATION) f(LALT) f(SPACE) f(RALT) f(RCTRL) \
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f(SEMICOLON) f(APOSTROPHE) f(RETURN) f(LSHIFT) f(Z) f(X) \
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f(UP) f(DOWN) f(LEFT) f(RIGHT) f(INSERT) f(DELETE) f(HOME) f(END) f(PAGEUP) f(PAGEDOWN)
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f(C) f(V) f(B) f(N) f(M) f(COMMA) f(PERIOD) f(SLASH) \
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f(RSHIFT) f(LCTRL) f(APPLICATION) f(LALT) \
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f(SPACE) f(RALT) f(RCTRL) f(UP) f(DOWN) \
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f(LEFT) f(RIGHT) f(INSERT) f(DELETE) \
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f(HOME) f(END) f(PAGEUP) f(PAGEDOWN)
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#define NEMU_KEY_NAME(k) NEMU_KEY_ ## k,
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#define NEMU_KEY_NAME(k) NEMU_KEY_##k,
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enum {
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enum { NEMU_KEY_NONE = 0, MAP(NEMU_KEYS, NEMU_KEY_NAME) };
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NEMU_KEY_NONE = 0,
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MAP(NEMU_KEYS, NEMU_KEY_NAME)
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};
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#define SDL_KEYMAP(k) keymap[SDL_SCANCODE_ ## k] = NEMU_KEY_ ## k;
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#define SDL_KEYMAP(k) keymap[SDL_SCANCODE_##k] = NEMU_KEY_##k;
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static uint32_t keymap[256] = {};
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static uint32_t keymap[256] = {};
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static void init_keymap() {
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static void init_keymap() { MAP(NEMU_KEYS, SDL_KEYMAP) }
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MAP(NEMU_KEYS, SDL_KEYMAP)
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}
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#define KEY_QUEUE_LEN 1024
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#define KEY_QUEUE_LEN 1024
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static int key_queue[KEY_QUEUE_LEN] = {};
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static int key_queue[KEY_QUEUE_LEN] = {};
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@ -92,9 +94,11 @@ void init_i8042() {
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i8042_data_port_base = (uint32_t *)new_space(4);
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i8042_data_port_base = (uint32_t *)new_space(4);
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i8042_data_port_base[0] = NEMU_KEY_NONE;
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i8042_data_port_base[0] = NEMU_KEY_NONE;
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#ifdef CONFIG_HAS_PORT_IO
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#ifdef CONFIG_HAS_PORT_IO
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add_pio_map ("keyboard", CONFIG_I8042_DATA_PORT, i8042_data_port_base, 4, i8042_data_io_handler);
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add_pio_map("keyboard", CONFIG_I8042_DATA_PORT, i8042_data_port_base, 4,
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i8042_data_io_handler);
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#else
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#else
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add_mmio_map("keyboard", CONFIG_I8042_DATA_MMIO, i8042_data_port_base, 4, i8042_data_io_handler);
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add_mmio_map("keyboard", CONFIG_I8042_DATA_MMIO, i8042_data_port_base, 4,
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i8042_data_io_handler);
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#endif
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#endif
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IFNDEF(CONFIG_TARGET_AM, init_keymap());
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IFNDEF(CONFIG_TARGET_AM, init_keymap());
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}
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}
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@ -16,6 +16,7 @@
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#include <assert.h>
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#include <assert.h>
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#include <debug.h>
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#include <debug.h>
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#include <device/map.h>
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#include <device/map.h>
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#include <generated/autoconf.h>
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#include <utils.h>
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#include <utils.h>
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/* http://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming */
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/* http://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming */
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@ -16,6 +16,7 @@
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#include <assert.h>
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#include <assert.h>
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#include <device/alarm.h>
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#include <device/alarm.h>
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#include <device/map.h>
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#include <device/map.h>
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#include <generated/autoconf.h>
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#include <utils.h>
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#include <utils.h>
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static uint32_t *rtc_port_base = NULL;
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static uint32_t *rtc_port_base = NULL;
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18
nemu/src/isa/riscv32/csr.c
Normal file
18
nemu/src/isa/riscv32/csr.c
Normal file
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@ -0,0 +1,18 @@
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#include <csr.h>
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void init_csr(csr_t csr) { memset(csr, 0, sizeof(word_t)); }
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void write_csr(csr_t csr, csr_addr_t csrnum, word_t value) {
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switch (csrnum) {
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default:
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csr[csrnum] = value;
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}
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}
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word_t read_csr(csr_t csr, csr_addr_t csrnum) {
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switch (csrnum) {
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// TODO: Implement csr read checks
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default:
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return csr[csrnum];
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}
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}
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@ -18,9 +18,13 @@
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#include <common.h>
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#include <common.h>
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#define CSR_SIZE (0x1000)
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typedef word_t csr_t[CSR_SIZE];
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typedef struct {
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typedef struct {
|
||||||
word_t gpr[MUXDEF(CONFIG_RVE, 16, 32)];
|
word_t gpr[MUXDEF(CONFIG_RVE, 16, 32)];
|
||||||
// word_t csr[MUXDEF(CONFIG_RVE, )]
|
csr_t csr;
|
||||||
vaddr_t pc;
|
vaddr_t pc;
|
||||||
} MUXDEF(CONFIG_RV64, riscv64_CPU_state, riscv32_CPU_state);
|
} MUXDEF(CONFIG_RV64, riscv64_CPU_state, riscv32_CPU_state);
|
||||||
|
|
||||||
|
|
|
@ -13,6 +13,7 @@
|
||||||
* See the Mulan PSL v2 for more details.
|
* See the Mulan PSL v2 for more details.
|
||||||
***************************************************************************************/
|
***************************************************************************************/
|
||||||
|
|
||||||
|
#include "isa.h"
|
||||||
#include "local-include/reg.h"
|
#include "local-include/reg.h"
|
||||||
#include "macro.h"
|
#include "macro.h"
|
||||||
#include "types.h"
|
#include "types.h"
|
||||||
|
@ -20,6 +21,7 @@
|
||||||
#include <cpu/cpu.h>
|
#include <cpu/cpu.h>
|
||||||
#include <cpu/decode.h>
|
#include <cpu/decode.h>
|
||||||
#include <cpu/ifetch.h>
|
#include <cpu/ifetch.h>
|
||||||
|
#include <csr.h>
|
||||||
#include <ftrace.h>
|
#include <ftrace.h>
|
||||||
#include <utils.h>
|
#include <utils.h>
|
||||||
|
|
||||||
|
@ -33,6 +35,8 @@ enum {
|
||||||
TYPE_S,
|
TYPE_S,
|
||||||
TYPE_B,
|
TYPE_B,
|
||||||
TYPE_J,
|
TYPE_J,
|
||||||
|
TYPE_CSR,
|
||||||
|
TYPE_CSRI,
|
||||||
TYPE_N, // none
|
TYPE_N, // none
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -66,6 +70,14 @@ enum {
|
||||||
*imm = SEXT(BITS(i, 31, 31), 1) << 20 | BITS(i, 30, 21) << 1 | \
|
*imm = SEXT(BITS(i, 31, 31), 1) << 20 | BITS(i, 30, 21) << 1 | \
|
||||||
BITS(i, 20, 20) << 11 | BITS(i, 19, 12) << 12; \
|
BITS(i, 20, 20) << 11 | BITS(i, 19, 12) << 12; \
|
||||||
} while (0)
|
} while (0)
|
||||||
|
#define csr() \
|
||||||
|
do { \
|
||||||
|
*src2 = BITS(i, 31, 20); \
|
||||||
|
} while (0)
|
||||||
|
#define uimm() \
|
||||||
|
do { \
|
||||||
|
*imm = BITS(i, 19, 15); \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
static void decode_operand(Decode *s, int *rd, word_t *src1, word_t *src2,
|
static void decode_operand(Decode *s, int *rd, word_t *src1, word_t *src2,
|
||||||
word_t *imm, int type) {
|
word_t *imm, int type) {
|
||||||
|
@ -98,6 +110,14 @@ static void decode_operand(Decode *s, int *rd, word_t *src1, word_t *src2,
|
||||||
src2R();
|
src2R();
|
||||||
immB();
|
immB();
|
||||||
break;
|
break;
|
||||||
|
case TYPE_CSR:
|
||||||
|
src1R();
|
||||||
|
csr();
|
||||||
|
break;
|
||||||
|
case TYPE_CSRI:
|
||||||
|
csr();
|
||||||
|
uimm();
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -249,6 +269,44 @@ static int decode_exec(Decode *s) {
|
||||||
INSTPAT("0000001 ????? ????? 111 ????? 01100 11", remu, R,
|
INSTPAT("0000001 ????? ????? 111 ????? 01100 11", remu, R,
|
||||||
R(rd) = src1 % src2);
|
R(rd) = src1 % src2);
|
||||||
|
|
||||||
|
// "Previledge"
|
||||||
|
// -- CSR instructions
|
||||||
|
INSTPAT(
|
||||||
|
"??????? ????? ????? 001 ????? 11100 11", csrrw, CSR, do {
|
||||||
|
R(rd) = read_csr(cpu.csr, src2);
|
||||||
|
write_csr(cpu.csr, src2, src1);
|
||||||
|
} while (0););
|
||||||
|
INSTPAT(
|
||||||
|
"??????? ????? ????? 010 ????? 11100 11", csrrs, CSR, do {
|
||||||
|
R(rd) = read_csr(cpu.csr, src2);
|
||||||
|
set_csr_bits(cpu.csr, src2, src1);
|
||||||
|
} while (0););
|
||||||
|
INSTPAT(
|
||||||
|
"??????? ????? ????? 011 ????? 11100 11", csrrc, CSR, do {
|
||||||
|
R(rd) = read_csr(cpu.csr, src2);
|
||||||
|
clear_csr_bits(cpu.csr, src2, src1);
|
||||||
|
} while (0););
|
||||||
|
INSTPAT(
|
||||||
|
"??????? ????? ????? 101 ????? 11100 11", csrrwi, CSRI, do {
|
||||||
|
R(rd) = read_csr(cpu.csr, src2);
|
||||||
|
write_csr(cpu.csr, src2, imm);
|
||||||
|
} while (0););
|
||||||
|
INSTPAT(
|
||||||
|
"??????? ????? ????? 110 ????? 11100 11", csrrsi, CSRI, do {
|
||||||
|
R(rd) = read_csr(cpu.csr, src2);
|
||||||
|
set_csr_bits(cpu.csr, src2, imm);
|
||||||
|
} while (0););
|
||||||
|
INSTPAT(
|
||||||
|
"??????? ????? ????? 111 ????? 11100 11", csrrci, CSRI, do {
|
||||||
|
R(rd) = read_csr(cpu.csr, src2);
|
||||||
|
clear_csr_bits(cpu.csr, src2, imm);
|
||||||
|
} while (0););
|
||||||
|
// -- Machine level
|
||||||
|
INSTPAT("0000000 00000 00000 000 00000 11100 11", ecall, N,
|
||||||
|
s->dnpc = isa_raise_intr(CauseEnvironmentCallFromMMode, cpu.pc));
|
||||||
|
INSTPAT("0011000 00010 00000 000 00000 11100 11", mret, N,
|
||||||
|
s->dnpc = read_csr(cpu.csr, MEPC));
|
||||||
|
|
||||||
INSTPAT("??????? ????? ????? ??? ????? ????? ??", inv, N, INV(s->pc));
|
INSTPAT("??????? ????? ????? ??? ????? ????? ??", inv, N, INV(s->pc));
|
||||||
INSTPAT_END();
|
INSTPAT_END();
|
||||||
|
|
||||||
|
|
29
nemu/src/isa/riscv32/local-include/csr.h
Normal file
29
nemu/src/isa/riscv32/local-include/csr.h
Normal file
|
@ -0,0 +1,29 @@
|
||||||
|
#ifndef __NEMU_CSR_H__
|
||||||
|
#define __NEMU_CSR_H__
|
||||||
|
#include <isa-def.h>
|
||||||
|
#include <types.h>
|
||||||
|
|
||||||
|
#define MSTATUS 0x300
|
||||||
|
#define MISA 0x301
|
||||||
|
#define MIE 0x304
|
||||||
|
#define MTVEC 0x305
|
||||||
|
#define MEPC 0x341
|
||||||
|
#define MCAUSE 0x342
|
||||||
|
|
||||||
|
enum { CauseEnvironmentCallFromMMode = 11 };
|
||||||
|
|
||||||
|
typedef uint16_t csr_addr_t;
|
||||||
|
|
||||||
|
void init_csr(csr_t csr);
|
||||||
|
|
||||||
|
/* macro for setting and clearing csr bits */
|
||||||
|
#define set_csr_bits(csr, reg, mask) \
|
||||||
|
write_csr(csr, reg, read_csr(csr, reg) | (mask))
|
||||||
|
|
||||||
|
#define clear_csr_bits(csr, reg, mask) \
|
||||||
|
write_csr(csr, reg, read_csr(csr, reg) & ~(mask))
|
||||||
|
|
||||||
|
void write_csr(csr_t csr, csr_addr_t csrnum, word_t value);
|
||||||
|
word_t read_csr(csr_t csr, csr_addr_t csrnum);
|
||||||
|
|
||||||
|
#endif // __NEMU_CSR_H__
|
|
@ -14,6 +14,7 @@
|
||||||
***************************************************************************************/
|
***************************************************************************************/
|
||||||
|
|
||||||
#include "local-include/reg.h"
|
#include "local-include/reg.h"
|
||||||
|
#include "csr.h"
|
||||||
#include "macro.h"
|
#include "macro.h"
|
||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
#include <gdbstub.h>
|
#include <gdbstub.h>
|
||||||
|
@ -51,11 +52,13 @@ word_t isa_reg_str2val(const char *s, bool *success) {
|
||||||
}
|
}
|
||||||
|
|
||||||
int isa_read_reg(void *args, int regno, size_t *reg_value) {
|
int isa_read_reg(void *args, int regno, size_t *reg_value) {
|
||||||
if (regno > 32) {
|
if (regno > 33) {
|
||||||
return EFAULT;
|
return EFAULT;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (regno == 32) {
|
if (regno == 33) {
|
||||||
|
*reg_value = cpu.csr[MTVEC];
|
||||||
|
} else if (regno == 32) {
|
||||||
*reg_value = cpu.pc;
|
*reg_value = cpu.pc;
|
||||||
} else {
|
} else {
|
||||||
*reg_value = cpu.gpr[regno];
|
*reg_value = cpu.gpr[regno];
|
||||||
|
@ -64,11 +67,13 @@ int isa_read_reg(void *args, int regno, size_t *reg_value) {
|
||||||
}
|
}
|
||||||
|
|
||||||
int isa_write_reg(void *args, int regno, size_t data) {
|
int isa_write_reg(void *args, int regno, size_t data) {
|
||||||
if (regno > 32) {
|
if (regno > 33) {
|
||||||
return EFAULT;
|
return EFAULT;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (regno == 32) {
|
if (regno == 33) {
|
||||||
|
cpu.csr[MTVEC] = data;
|
||||||
|
} else if (regno == 32) {
|
||||||
cpu.pc = data;
|
cpu.pc = data;
|
||||||
} else {
|
} else {
|
||||||
cpu.gpr[regno] = data;
|
cpu.gpr[regno] = data;
|
||||||
|
@ -76,6 +81,6 @@ int isa_write_reg(void *args, int regno, size_t data) {
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
__EXPORT arch_info_t isa_arch_info = {.reg_num = 32,
|
__EXPORT arch_info_t isa_arch_info = {.reg_num = 33,
|
||||||
.reg_byte = MUXDEF(CONFIG_RV64, 8, 4),
|
.reg_byte = MUXDEF(CONFIG_RV64, 8, 4),
|
||||||
.target_desc = TARGET_RV32};
|
.target_desc = TARGET_RV32};
|
||||||
|
|
|
@ -13,16 +13,14 @@
|
||||||
* See the Mulan PSL v2 for more details.
|
* See the Mulan PSL v2 for more details.
|
||||||
***************************************************************************************/
|
***************************************************************************************/
|
||||||
|
|
||||||
|
#include <csr.h>
|
||||||
#include <isa.h>
|
#include <isa.h>
|
||||||
|
|
||||||
word_t isa_raise_intr(word_t NO, vaddr_t epc) {
|
word_t isa_raise_intr(word_t NO, vaddr_t epc) {
|
||||||
/* TODO: Trigger an interrupt/exception with ``NO''.
|
write_csr(cpu.csr, MEPC, epc);
|
||||||
* Then return the address of the interrupt/exception vector.
|
write_csr(cpu.csr, MCAUSE, NO);
|
||||||
*/
|
|
||||||
|
|
||||||
return 0;
|
return read_csr(cpu.csr, MTVEC);
|
||||||
}
|
}
|
||||||
|
|
||||||
word_t isa_query_intr() {
|
word_t isa_query_intr() { return INTR_EMPTY; }
|
||||||
return INTR_EMPTY;
|
|
||||||
}
|
|
||||||
|
|
|
@ -59,6 +59,11 @@ static void nemu_is_stopped(gdb_action_t *act, breakpoint_t *stopped_at) {
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case NEMU_GDB_INTERRUPT:
|
||||||
|
act->reason = gdb_action_t::ACT_BREAKPOINT;
|
||||||
|
act->data = cpu.pc;
|
||||||
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
act->reason = gdb_action_t::ACT_SHUTDOWN;
|
act->reason = gdb_action_t::ACT_SHUTDOWN;
|
||||||
act->data = nemu_state.halt_ret;
|
act->data = nemu_state.halt_ret;
|
||||||
|
@ -103,7 +108,7 @@ __EXPORT bool nemu_del_bp(void *args, size_t addr, bp_type_t type) {
|
||||||
}
|
}
|
||||||
|
|
||||||
__EXPORT void nemu_on_interrupt(void *args) {
|
__EXPORT void nemu_on_interrupt(void *args) {
|
||||||
// fputs("Not implemented", stderr);
|
nemu_state.state = NEMU_GDB_INTERRUPT;
|
||||||
}
|
}
|
||||||
|
|
||||||
__EXPORT int nemu_read_reg(void *args, int regno, size_t *data) {
|
__EXPORT int nemu_read_reg(void *args, int regno, size_t *data) {
|
||||||
|
@ -121,7 +126,8 @@ static struct target_ops nemu_gdbstub_ops = {.cont = nemu_cont,
|
||||||
.write_mem = nemu_write_mem,
|
.write_mem = nemu_write_mem,
|
||||||
.set_bp = nemu_set_bp,
|
.set_bp = nemu_set_bp,
|
||||||
.del_bp = nemu_del_bp,
|
.del_bp = nemu_del_bp,
|
||||||
.on_interrupt = NULL};
|
.on_interrupt = nemu_on_interrupt,
|
||||||
|
.monitor = NULL};
|
||||||
static DbgState *pdbg;
|
static DbgState *pdbg;
|
||||||
static gdbstub_t gdbstub_priv;
|
static gdbstub_t gdbstub_priv;
|
||||||
const char SOCKET_ADDR[] = "/tmp/gdbstub-nemu.sock";
|
const char SOCKET_ADDR[] = "/tmp/gdbstub-nemu.sock";
|
||||||
|
@ -152,7 +158,7 @@ __EXPORT void nemu_init(void *args) {
|
||||||
|
|
||||||
int gdbstub_loop() {
|
int gdbstub_loop() {
|
||||||
if (!gdbstub_init(&gdbstub_priv, &nemu_gdbstub_ops,
|
if (!gdbstub_init(&gdbstub_priv, &nemu_gdbstub_ops,
|
||||||
(arch_info_t)isa_arch_info, SOCKET_ADDR)) {
|
(arch_info_t)isa_arch_info, NULL, SOCKET_ADDR)) {
|
||||||
return EINVAL;
|
return EINVAL;
|
||||||
}
|
}
|
||||||
printf("Waiting for gdb connection at %s", SOCKET_ADDR);
|
printf("Waiting for gdb connection at %s", SOCKET_ADDR);
|
||||||
|
|
Loading…
Reference in a new issue