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> sim RTL

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ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 20:21:56  up  23:19,  2 users,  load average: 0.30, 0.29, 0.42
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tracer-ysyx 2023-12-23 20:21:56 +08:00 committed by xinyangli
parent c1c37d64a4
commit 88a55f87ea
1 changed files with 1 additions and 1 deletions
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2
npc/Makefile
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@ -8,7 +8,7 @@ VERILATOR_FLAGS := --cc --exe
all: sim all: sim
sim: VERILATOR_FLAGS += --trace sim: VERILATOR_FLAGS += --trace
sim: $(VSRC) $(CPPSRC) $(SUBMAKE) sim: $(VSRC) $(CPPSRC) $(OBJDIR)/Vexample
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!! $(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Running" $(OBJDIR)/Vexample "..." @echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================" @echo "================================"