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> sim RTL

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ysyx_22040000 李心杨
Linux calcite 6.1.65 #1-NixOS SMP PREEMPT_DYNAMIC Sun Dec  3 06:32:13 UTC 2023 x86_64 GNU/Linux
 20:00:32  up  22:58,  2 users,  load average: 0.75, 0.70, 0.58
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tracer-ysyx 2023-12-23 20:00:32 +08:00 committed by xinyangli
parent 2d510e0aa3
commit 764d95f844
1 changed files with 4 additions and 0 deletions
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4
npc/Makefile
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@ -10,6 +10,10 @@ sim: all
$(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!!
@echo "Running" $(OBJDIR)/Vexample "..."
@echo "================================"
@$(OBJDIR)/Vexample +trace off
trace: all
$(call git_commit, "trace RTL") # DO NOT REMOVE THIS LINE!!!
@$(OBJDIR)/Vexample