diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index a27983e..9443937 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -1,6 +1,7 @@
 package npc
 
 import chisel3._
+import chisel3.utils.{MuxLookup}
 import chisel3.stage.ChiselOption
 
 class RegisterFile(readPorts: Int) extends Module {
@@ -34,7 +35,7 @@ class ALUGenerator(width: Int) extends Module {
     val out = Output(UInt(width.W))
   })
 
-  val adder_b = fill(width)(io.op(0)) ^ io.b  // take (-b) if sub
+  val adder_b = Fill(width)(io.op(0)) ^ io.b  // take (-b) if sub
   val add = io.a + adder_b
   val and = io.a & io.b
   val not = ~io.a