> configure(npc)

ysyx_22040000 李心杨
 Linux calcite 6.6.19 #1-NixOS SMP PREEMPT_DYNAMIC Fri Mar  1 12:35:11 UTC 2024 x86_64 GNU/Linux
  13:34:46  up   3:10,  2 users,  load average: 0.77, 1.10, 1.08
This commit is contained in:
tracer-ysyx 2024-03-13 13:34:46 +08:00 committed by xinyangli
parent 545c64c479
commit 6be0953168
5 changed files with 6 additions and 503 deletions

View file

@ -5,11 +5,11 @@
"systems": "systems" "systems": "systems"
}, },
"locked": { "locked": {
"lastModified": 1710146030, "lastModified": 1709126324,
"narHash": "sha256-SZ5L6eA7HJ/nmkzGG7/ISclqe6oZdOZTNoesiInkXPQ=", "narHash": "sha256-q6EQdSeUZOG26WelxqkmR7kArjgWCdw5sfJVHPH/7j8=",
"owner": "numtide", "owner": "numtide",
"repo": "flake-utils", "repo": "flake-utils",
"rev": "b1d9ab70662946ef0850d488da1c9019f3a9752a", "rev": "d465f4819400de7c8d874d50b982301f28a84605",
"type": "github" "type": "github"
}, },
"original": { "original": {
@ -20,11 +20,11 @@
}, },
"nixpkgs": { "nixpkgs": {
"locked": { "locked": {
"lastModified": 1709961763, "lastModified": 1709237383,
"narHash": "sha256-6H95HGJHhEZtyYA3rIQpvamMKAGoa8Yh2rFV29QnuGw=", "narHash": "sha256-cy6ArO4k5qTx+l5o+0mL9f5fa86tYUX3ozE1S+Txlds=",
"owner": "NixOS", "owner": "NixOS",
"repo": "nixpkgs", "repo": "nixpkgs",
"rev": "3030f185ba6a4bf4f18b87f345f104e6a6961f34", "rev": "1536926ef5621b09bba54035ae2bb6d806d72ac8",
"type": "github" "type": "github"
}, },
"original": { "original": {

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@ -1,5 +1 @@
top=Flow top=Flow
io_sw_0 (SW0)
io_sw_1 (SW1)
io_out (LD0)

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@ -1,4 +0,0 @@
[{
"class": "firrtl.transforms.DontTouchAnnotation",
"target": "~Flow|Control"
}]

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@ -94,7 +94,6 @@ class Flow extends Module {
ram.readPorts(0).enable := true.B ram.readPorts(0).enable := true.B
ram.readPorts(0).address := pc.out - 0x80000000L.U ram.readPorts(0).address := pc.out - 0x80000000L.U
val inst = ram.readPorts(0).data val inst = ram.readPorts(0).data
printf(cf"$inst\n")
import control.pc.SrcSelect._ import control.pc.SrcSelect._

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@ -1,488 +0,0 @@
$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module TOP $end
$var wire 1 N clock $end
$var wire 1 O reset $end
$scope module Flow $end
$var wire 1 N clock $end
$var wire 1 O reset $end
$scope module alu $end
$var wire 4 P control_op [3:0] $end
$var wire 1 Q control_src $end
$var wire 32 # in_a_0 [31:0] $end
$var wire 32 $ in_a_1 [31:0] $end
$var wire 32 % in_b [31:0] $end
$var wire 32 & out_result [31:0] $end
$upscope $end
$scope module control $end
$var wire 1 Q reg_writeEnable $end
$var wire 1 R reg_writeSelect $end
$var wire 1 R pc_srcSelect $end
$var wire 4 P alu_op [3:0] $end
$var wire 1 Q alu_src $end
$var wire 8 S out [7:0] $end
$upscope $end
$scope module pc $end
$var wire 1 N clock $end
$var wire 1 O reset $end
$var wire 1 R control_srcSelect $end
$var wire 32 ' in_pcSrcs_0 [31:0] $end
$var wire 32 & in_pcSrcs_1 [31:0] $end
$var wire 32 ( out [31:0] $end
$var wire 32 ( pc [31:0] $end
$upscope $end
$scope module ram_mem_ext $end
$var wire 10 ) R0_addr [9:0] $end
$var wire 1 Q R0_en $end
$var wire 1 N R0_clk $end
$var wire 32 * R0_data [31:0] $end
$upscope $end
$scope module reg_core $end
$var wire 1 N clock $end
$var wire 1 O reset $end
$var wire 1 Q writePort_enable $end
$var wire 5 + writePort_addr [4:0] $end
$var wire 32 & writePort_data [31:0] $end
$var wire 5 , readPorts_0_addr [4:0] $end
$var wire 32 # readPorts_0_data [31:0] $end
$var wire 5 - readPorts_1_addr [4:0] $end
$var wire 32 % readPorts_1_data [31:0] $end
$var wire 32 . regFile_0 [31:0] $end
$var wire 32 / regFile_1 [31:0] $end
$var wire 32 0 regFile_2 [31:0] $end
$var wire 32 1 regFile_3 [31:0] $end
$var wire 32 2 regFile_4 [31:0] $end
$var wire 32 3 regFile_5 [31:0] $end
$var wire 32 4 regFile_6 [31:0] $end
$var wire 32 5 regFile_7 [31:0] $end
$var wire 32 6 regFile_8 [31:0] $end
$var wire 32 7 regFile_9 [31:0] $end
$var wire 32 8 regFile_10 [31:0] $end
$var wire 32 9 regFile_11 [31:0] $end
$var wire 32 : regFile_12 [31:0] $end
$var wire 32 ; regFile_13 [31:0] $end
$var wire 32 < regFile_14 [31:0] $end
$var wire 32 = regFile_15 [31:0] $end
$var wire 32 > regFile_16 [31:0] $end
$var wire 32 ? regFile_17 [31:0] $end
$var wire 32 @ regFile_18 [31:0] $end
$var wire 32 A regFile_19 [31:0] $end
$var wire 32 B regFile_20 [31:0] $end
$var wire 32 C regFile_21 [31:0] $end
$var wire 32 D regFile_22 [31:0] $end
$var wire 32 E regFile_23 [31:0] $end
$var wire 32 F regFile_24 [31:0] $end
$var wire 32 G regFile_25 [31:0] $end
$var wire 32 H regFile_26 [31:0] $end
$var wire 32 I regFile_27 [31:0] $end
$var wire 32 J regFile_28 [31:0] $end
$var wire 32 K regFile_29 [31:0] $end
$var wire 32 L regFile_30 [31:0] $end
$var wire 32 M regFile_31 [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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