build: fix rules and dependencies
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4bc4c34af4
commit
6ab5d4c156
7 changed files with 18 additions and 26 deletions
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@ -10,7 +10,7 @@ enable_testing()
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list(APPEND CMAKE_MODULE_PATH ${PROJECT_SOURCE_DIR}/cmake)
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# -- Build options
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option(BUILD_USE_BLOOP "Whether to use bloop to speed up elaborate" ON)
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option(BUILD_USE_BLOOP "Whether to use bloop to speed up elaborate" OFF)
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option(BUILD_SIM_TARGET "Whether to build verilator simulation binary" ON)
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cmake_dependent_option(BUILD_SIM_NVBOARD_TARGET "Whether to build nvboard target" OFF "BUILD_SIM_TARGET" OFF)
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option(ENABLE_YSYX_GIT_TRACKER "Ysyx tracker support" ON)
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@ -34,8 +34,6 @@ if(BUILD_SIM_NVBOARD_TARGET)
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find_package(SDL2_image REQUIRED)
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endif()
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find_package(CLI11 CONFIG REQUIRED)
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# TODO: Not required
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find_package(LLVM CONFIG REQUIRED)
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option(ENABLE_SDB "Enable simple debugger" ON)
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@ -47,14 +45,11 @@ find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h)
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set(SCALA_CORE "${CMAKE_CURRENT_SOURCE_DIR}/core")
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set(CHISEL_MODULE_CLASS "${CMAKE_PROJECT_NAME}.${TOPMODULE}")
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# Verilog files are generted in CHISEL_OUTPUT_TMP_DIR and copy to
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# CHISEL_OUTPUT_DIR if content changes
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set(CHISEL_OUTPUT_DIR ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc)
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set(CHISEL_OUTPUT_TMP_DIR ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc_tmp)
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set(CHISEL_OUTPUT_VERILATOR_CONF ${CHISEL_OUTPUT_DIR}/conf.vlt)
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set(CHISEL_OUTPUT_TOPMODULE ${CHISEL_OUTPUT_DIR}/${TOPMODULE}.sv)
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set(CHISEL_EMIT_ARGS "--target-dir ${CHISEL_OUTPUT_TMP_DIR}")
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set(CHISEL_EMIT_ARGS "--target-dir ${CHISEL_OUTPUT_DIR}")
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# -- Build NVBoard executable
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if(BUILD_SIM_NVBOARD_TARGET)
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@ -19,9 +19,8 @@ if(BUILD_USE_BLOOP)
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string(REPLACE " " ";" CHISEL_EMIT_ARGS_LIST ${CHISEL_EMIT_ARGS})
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list(TRANSFORM CHISEL_EMIT_ARGS_LIST PREPEND "--args;")
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add_custom_command(
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OUTPUT ${CHISEL_OUTPUT_TOPMODULE}
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COMMAND bloop run root ${CHISEL_EMIT_ARGS_LIST}
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COMMAND ${CMAKE_COMMAND} -E copy_directory_if_different ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR}
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OUTPUT ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF}
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COMMAND bloop run --no-color root ${CHISEL_EMIT_ARGS_LIST}
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WORKING_DIRECTORY ${SCALA_CORE}
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DEPENDS ${CHISEL_DEPENDENCY}
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COMMAND_EXPAND_LISTS
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@ -36,9 +35,8 @@ else()
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set(CHISEL_TARGET sbt_${TOPMODULE})
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set(CHISEL_TEST_TARGET sbt_${TOPMODULE}_test)
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add_custom_command(
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OUTPUT ${CHISEL_OUTPUT_TOPMODULE}
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OUTPUT ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF}
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COMMAND sbt "run ${CHISEL_EMIT_ARGS}"
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COMMAND ${CMAKE_COMMAND} -E copy_directory_if_different ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR}
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WORKING_DIRECTORY ${SCALA_CORE}
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DEPENDS ${CHISEL_DEPENDENCY}
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VERBATIM
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@ -51,13 +49,10 @@ else()
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)
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endif()
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if(NOT EXISTS ${CHISEL_OUTPUT_DIR})
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if(NOT EXISTS ${CHISEL_OUTPUT_TOPMODULE})
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# Probably cold build, generate verilog at configure time to produce top module file
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execute_process(
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COMMAND sbt "run ${CHISEL_EMIT_ARGS}"
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WORKING_DIRECTORY ${SCALA_CORE}
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)
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execute_process(
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COMMAND ${CMAKE_COMMAND} -E copy_directory ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR}
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)
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endif()
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@ -409,7 +409,6 @@ class Flow extends Module {
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reg.in.rs(1) := inst(24, 20) // rs2
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// TODO: Bulk connection here
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// FIXME: The following 2 lines won't compile with bloop
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ram.io.clock := clock
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ram.io.reset := reset
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ram.io.writeAddr := alu.out.result
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@ -2,7 +2,7 @@ include(ChiselBuild)
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add_executable(V${TOPMODULE} config.cpp main.cpp)
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target_link_libraries(V${TOPMODULE} PRIVATE sdb)
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verilate(V${TOPMODULE} TRACE COVERAGE THREADS
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verilate(V${TOPMODULE} TRACE THREADS
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TOP_MODULE ${TOPMODULE}
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PREFIX V${TOPMODULE}
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SOURCES ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF}
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@ -1 +0,0 @@
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@ -1,6 +1,7 @@
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find_package(Readline REQUIRED)
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find_package(FLEX REQUIRED)
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find_package(BISON REQUIRED)
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find_package(LLVM CONFIG REQUIRED)
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set(PARSER_DIR "${CMAKE_CURRENT_BINARY_DIR}")
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set(LEXER_OUT "${PARSER_DIR}/lexer.c")
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set(PARSER_OUT "${PARSER_DIR}/parser.c")
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@ -8,8 +9,8 @@ flex_target(LEXER addrexp.l "${LEXER_OUT}" DEFINES_FILE "${PARSER_DIR}/addrexp_l
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bison_target(PARSER addrexp.y "${PARSER_OUT}" DEFINES_FILE "${PARSER_DIR}/addrexp.h")
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add_flex_bison_dependency(LEXER PARSER)
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add_library(sdb sdb.cpp console.cpp disasm.cpp "${LEXER_OUT}" "${PARSER_OUT}")
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llvm_map_components_to_libnames(LLVM_LIBS ${LLVM_TARGETS_TO_BUILD})
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add_library(sdb OBJECT sdb.cpp console.cpp disasm.cpp "${LEXER_OUT}" "${PARSER_OUT}")
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llvm_map_components_to_libnames(LLVM_LIBS core target asmparser riscvasmparser riscvdesc riscvdisassembler riscvinfo riscvtargetmca)
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target_link_libraries(sdb PUBLIC ${LLVM_LIBS})
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target_link_libraries(sdb PRIVATE ${Readline_LIBRARY})
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target_include_directories(sdb PRIVATE ${PARSER_DIR})
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@ -25,11 +25,14 @@
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#endif
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Disassembler::Disassembler(std::string triple) : triple(triple) {
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llvm::InitializeAllTargetInfos();
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llvm::InitializeAllTargetMCs();
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llvm::InitializeAllAsmParsers();
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llvm::InitializeAllDisassemblers();
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// llvm::InitializeAllTargetInfos();
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// llvm::InitializeAllTargetMCs();
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// llvm::InitializeAllAsmParsers();
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// llvm::InitializeAllDisassemblers();
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LLVMInitializeRISCVTargetInfo();
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LLVMInitializeRISCVTargetMC();
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LLVMInitializeRISCVAsmParser();
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LLVMInitializeRISCVDisassembler();
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std::string errstr;
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llvm::MCInstrInfo *gMII = nullptr;
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