build: fix rules and dependencies

npc/CMakeLists.txt

@@ -10,7 +10,7 @@ enable_testing()
 list(APPEND CMAKE_MODULE_PATH ${PROJECT_SOURCE_DIR}/cmake)
 
 # -- Build options
-option(BUILD_USE_BLOOP "Whether to use bloop to speed up elaborate" ON)
+option(BUILD_USE_BLOOP "Whether to use bloop to speed up elaborate" OFF)
 option(BUILD_SIM_TARGET "Whether to build verilator simulation binary" ON)
 cmake_dependent_option(BUILD_SIM_NVBOARD_TARGET "Whether to build nvboard target" OFF "BUILD_SIM_TARGET" OFF)
 option(ENABLE_YSYX_GIT_TRACKER "Ysyx tracker support" ON)
@@ -34,8 +34,6 @@ if(BUILD_SIM_NVBOARD_TARGET)
   find_package(SDL2_image REQUIRED)
 endif()
 find_package(CLI11 CONFIG REQUIRED)
-# TODO: Not required
-find_package(LLVM CONFIG REQUIRED)
 
 option(ENABLE_SDB "Enable simple debugger" ON)
 
@@ -47,14 +45,11 @@ find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h)
 set(SCALA_CORE "${CMAKE_CURRENT_SOURCE_DIR}/core")
 set(CHISEL_MODULE_CLASS "${CMAKE_PROJECT_NAME}.${TOPMODULE}")
 
-# Verilog files are generted in CHISEL_OUTPUT_TMP_DIR and copy to
-# CHISEL_OUTPUT_DIR if content changes
 set(CHISEL_OUTPUT_DIR ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc)
-set(CHISEL_OUTPUT_TMP_DIR ${CMAKE_CURRENT_BINARY_DIR}/${TOPMODULE}/vsrc_tmp)
 
 set(CHISEL_OUTPUT_VERILATOR_CONF ${CHISEL_OUTPUT_DIR}/conf.vlt)
 set(CHISEL_OUTPUT_TOPMODULE ${CHISEL_OUTPUT_DIR}/${TOPMODULE}.sv)
-set(CHISEL_EMIT_ARGS "--target-dir ${CHISEL_OUTPUT_TMP_DIR}")
+set(CHISEL_EMIT_ARGS "--target-dir ${CHISEL_OUTPUT_DIR}")
 
 # -- Build NVBoard executable
 if(BUILD_SIM_NVBOARD_TARGET)

npc/cmake/ChiselBuild.cmake

@@ -19,9 +19,8 @@ if(BUILD_USE_BLOOP)
   string(REPLACE " " ";" CHISEL_EMIT_ARGS_LIST ${CHISEL_EMIT_ARGS})
   list(TRANSFORM CHISEL_EMIT_ARGS_LIST PREPEND "--args;")
   add_custom_command(
-    OUTPUT ${CHISEL_OUTPUT_TOPMODULE}
-    COMMAND bloop run root ${CHISEL_EMIT_ARGS_LIST}
-    COMMAND ${CMAKE_COMMAND} -E copy_directory_if_different ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR}
+    OUTPUT ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF}
+    COMMAND bloop run --no-color root ${CHISEL_EMIT_ARGS_LIST}
     WORKING_DIRECTORY ${SCALA_CORE}
     DEPENDS ${CHISEL_DEPENDENCY}
     COMMAND_EXPAND_LISTS
@@ -36,9 +35,8 @@ else()
   set(CHISEL_TARGET sbt_${TOPMODULE})
   set(CHISEL_TEST_TARGET sbt_${TOPMODULE}_test)
   add_custom_command(
-    OUTPUT ${CHISEL_OUTPUT_TOPMODULE}
+    OUTPUT ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF}
     COMMAND sbt "run ${CHISEL_EMIT_ARGS}"
-    COMMAND ${CMAKE_COMMAND} -E copy_directory_if_different ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR}
     WORKING_DIRECTORY ${SCALA_CORE}
     DEPENDS ${CHISEL_DEPENDENCY}
     VERBATIM
@@ -51,13 +49,10 @@ else()
   )
 endif()
 
-if(NOT EXISTS ${CHISEL_OUTPUT_DIR})
+if(NOT EXISTS ${CHISEL_OUTPUT_TOPMODULE})
   # Probably cold build, generate verilog at configure time to produce top module file
   execute_process(
     COMMAND sbt "run ${CHISEL_EMIT_ARGS}"
     WORKING_DIRECTORY ${SCALA_CORE}
   )
-  execute_process(
-    COMMAND ${CMAKE_COMMAND} -E copy_directory ${CHISEL_OUTPUT_TMP_DIR} ${CHISEL_OUTPUT_DIR}
-  )
 endif()

npc/core/src/main/scala/top/FlowMain.scala

@@ -409,7 +409,6 @@ class Flow extends Module {
   reg.in.rs(1) := inst(24, 20) // rs2
 
   // TODO: Bulk connection here
-  // FIXME: The following 2 lines won't compile with bloop
   ram.io.clock := clock
   ram.io.reset := reset
   ram.io.writeAddr := alu.out.result

npc/csrc/Flow/CMakeLists.txt

@@ -2,7 +2,7 @@ include(ChiselBuild)
 add_executable(V${TOPMODULE} config.cpp main.cpp)
 target_link_libraries(V${TOPMODULE} PRIVATE sdb)
 
-verilate(V${TOPMODULE} TRACE COVERAGE THREADS
+verilate(V${TOPMODULE} TRACE THREADS
   TOP_MODULE ${TOPMODULE}
   PREFIX V${TOPMODULE}
   SOURCES ${CHISEL_OUTPUT_TOPMODULE} ${CHISEL_OUTPUT_VERILATOR_CONF}

npc/utils/disasm/CMakeLists.txt

@@ -1 +0,0 @@
-

npc/utils/sdb/CMakeLists.txt

@@ -1,6 +1,7 @@
 find_package(Readline REQUIRED)
 find_package(FLEX REQUIRED)
 find_package(BISON REQUIRED)
+find_package(LLVM CONFIG REQUIRED)
 set(PARSER_DIR "${CMAKE_CURRENT_BINARY_DIR}")
 set(LEXER_OUT "${PARSER_DIR}/lexer.c")
 set(PARSER_OUT "${PARSER_DIR}/parser.c")
@@ -8,8 +9,8 @@ flex_target(LEXER addrexp.l "${LEXER_OUT}" DEFINES_FILE "${PARSER_DIR}/addrexp_l
 bison_target(PARSER addrexp.y "${PARSER_OUT}" DEFINES_FILE "${PARSER_DIR}/addrexp.h")
 add_flex_bison_dependency(LEXER PARSER)
 
-add_library(sdb sdb.cpp console.cpp disasm.cpp "${LEXER_OUT}" "${PARSER_OUT}")
-llvm_map_components_to_libnames(LLVM_LIBS ${LLVM_TARGETS_TO_BUILD})
+add_library(sdb OBJECT sdb.cpp console.cpp disasm.cpp "${LEXER_OUT}" "${PARSER_OUT}")
+llvm_map_components_to_libnames(LLVM_LIBS core target asmparser riscvasmparser riscvdesc riscvdisassembler riscvinfo riscvtargetmca)
 target_link_libraries(sdb PUBLIC ${LLVM_LIBS})
 target_link_libraries(sdb PRIVATE ${Readline_LIBRARY})
 target_include_directories(sdb PRIVATE ${PARSER_DIR})

npc/utils/sdb/disasm.cpp

@@ -25,11 +25,14 @@
 #endif
 
 Disassembler::Disassembler(std::string triple) : triple(triple) {
-  llvm::InitializeAllTargetInfos();
-  llvm::InitializeAllTargetMCs();
-  llvm::InitializeAllAsmParsers();
-  llvm::InitializeAllDisassemblers();
-
+  // llvm::InitializeAllTargetInfos();
+  // llvm::InitializeAllTargetMCs();
+  // llvm::InitializeAllAsmParsers();
+  // llvm::InitializeAllDisassemblers();
+  LLVMInitializeRISCVTargetInfo();
+  LLVMInitializeRISCVTargetMC();
+  LLVMInitializeRISCVAsmParser();
+  LLVMInitializeRISCVDisassembler();
   std::string errstr;
 
   llvm::MCInstrInfo *gMII = nullptr;