diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index 5644090..00e67c5 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -13,7 +13,7 @@ class Switch extends Module {
   io.out := io.sw(0) ^ io.sw(1)
 }
 
-import npc.util.{PS2Port, KeyboardController, SegGenerator}
+import npc.util.{PS2Port, KeyboardController, SegControllerGenerator}
 
 class Keyboard extends Module {
   val io = IO(new Bundle {
@@ -21,7 +21,7 @@ class Keyboard extends Module {
     val segs = Output(Vec(8, UInt(8.W)))
   })
 
-  val seg_handler = Module(new SegGenerator(seg_count = 8))
+  val seg_handler = Module(new SegControllerGenerator(seg_count = 8))
   val keyboard_controller = Module(new KeyboardController)
 
   seg_handler.io.keycode <> keyboard_controller.io.out
@@ -30,4 +30,3 @@ class Keyboard extends Module {
   io.segs := seg_handler.io.segs
 }
 
-class SegHandler extends SegGenerator(8) { }
diff --git a/npc/core/src/main/scala/SegGenerator.scala b/npc/core/src/main/scala/SegControllerGenerator.scala
similarity index 74%
rename from npc/core/src/main/scala/SegGenerator.scala
rename to npc/core/src/main/scala/SegControllerGenerator.scala
index 4a5efaf..ca6c44f 100644
--- a/npc/core/src/main/scala/SegGenerator.scala
+++ b/npc/core/src/main/scala/SegControllerGenerator.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.util.log2Ceil
 
-class SegGenerator(seg_count: Int) extends Module {
+class SegControllerGenerator(seg_count: Int) extends Module {
   val io = IO(new Bundle {
     val keycode = Flipped(Decoupled(UInt(8.W)))
     val segs = Output(Vec(seg_count, UInt(8.W)))
@@ -32,16 +32,30 @@ class SegGenerator(seg_count: Int) extends Module {
     0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
   ).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
 
-  val keycode = RegEnable(io.keycode.bits, io.keycode.ready && io.keycode.valid)
+  val keycode = RegInit(0.U(8.W))
+  val counter = Counter(0xFF)
+  val release_state = RegInit(Bool(), false.B)
+  when(io.keycode.ready && io.keycode.valid) {
+    when(io.keycode.bits === 0xF0.U) {
+      release_state := true.B
+    }.elsewhen(!release_state) {
+      keycode := io.keycode.bits
+      counter.inc()
+    }.otherwise{
+      // Release code on io.keycode.bits
+      release_state := false.B
+    }
+  }
+
   val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
   val keycode_seg = keycode_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
+
   val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
   val ascii_digits = VecInit(ascii(3,0)) ++ VecInit(ascii(6,4))
   val ascii_seg = ascii_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
-  val (counter, _) = Counter(io.keycode.valid && io.keycode.ready && io.keycode.bits =/= keycode, 0xFF)
-  val count_digits = VecInit(counter(3,0)) ++ VecInit(counter(7,4))
-  val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
 
+  val count_digits = VecInit(counter.value(3,0)) ++ VecInit(counter.value(7,4))
+  val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
   seg_regs := keycode_seg ++ ascii_seg ++ count_seg ++ Seq(0xFF.U, 0xFF.U)
 
   io.segs := seg_regs