xin/ysyx-workbench
1
0
Fork 0
Code Issues Pull requests 1 Projects Releases Packages Wiki Activity Actions

> sim RTL

Browse source 
ysyx_22040000 李心杨
Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
 13:43:05  up  22:22,  2 users,  load average: 1.05, 0.90, 0.86
This commit is contained in:
tracer-ysyx 2024-01-01 13:43:05 +08:00 committed by xinyangli
parent 419fbdb941
commit 6615352b77
1 changed files with 5 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
npc/csrc/main.cpp
View file

@ -4,12 +4,9 @@
#include <verilated.h>
#include <verilated_vcd_c.h>
#include <Vexample.h>
#include <nvboard.h>
const int MAX_SIM_TIME=100;
void nvboard_bind_all_pins(Vexample* top);
int main(int argc, char **argv, char **env) {
int sim_time = 0;
Verilated::commandArgs(argc, argv);
@ -17,20 +14,16 @@ int main(int argc, char **argv, char **env) {
Verilated::traceEverOn(true);
VerilatedVcdC *m_trace = new VerilatedVcdC;
nvboard_bind_all_pins(top);
nvboard_init();
#ifdef VERILATOR_TRACE
top->trace(m_trace, 5);
m_trace->open("waveform.vcd");
#endif
// for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
while (true) {
nvboard_update();
// CData sw = rand() & 0b11;
// top->sw = sw;
for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
CData sw = rand() & 0b11;
top->sw = sw;
top->eval();
// printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr);
// assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) );
printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr);
assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) );
#ifdef VERILATOR_TRACE
m_trace->dump(sim_time);
#endif