> sim RTL
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 13:43:05 up 22:22, 2 users, load average: 1.05, 0.90, 0.86
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1 changed files with 5 additions and 12 deletions
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@ -4,12 +4,9 @@
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#include <verilated.h>
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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#include <verilated_vcd_c.h>
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#include <Vexample.h>
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#include <Vexample.h>
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#include <nvboard.h>
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const int MAX_SIM_TIME=100;
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const int MAX_SIM_TIME=100;
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void nvboard_bind_all_pins(Vexample* top);
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int main(int argc, char **argv, char **env) {
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int main(int argc, char **argv, char **env) {
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int sim_time = 0;
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int sim_time = 0;
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Verilated::commandArgs(argc, argv);
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Verilated::commandArgs(argc, argv);
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@ -17,20 +14,16 @@ int main(int argc, char **argv, char **env) {
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Verilated::traceEverOn(true);
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Verilated::traceEverOn(true);
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VerilatedVcdC *m_trace = new VerilatedVcdC;
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VerilatedVcdC *m_trace = new VerilatedVcdC;
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nvboard_bind_all_pins(top);
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nvboard_init();
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#ifdef VERILATOR_TRACE
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#ifdef VERILATOR_TRACE
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top->trace(m_trace, 5);
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top->trace(m_trace, 5);
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m_trace->open("waveform.vcd");
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m_trace->open("waveform.vcd");
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#endif
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#endif
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// for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
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for (sim_time = 0; sim_time < MAX_SIM_TIME; sim_time++) {
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while (true) {
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CData sw = rand() & 0b11;
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nvboard_update();
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top->sw = sw;
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// CData sw = rand() & 0b11;
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// top->sw = sw;
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top->eval();
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top->eval();
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// printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr);
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printf("sw0 = %d, sw1 = %d, ledr = %d\n", sw & 0b1, sw >> 1, top->ledr);
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// assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) );
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assert(top->ledr == ((sw >> 1) ^ (sw & 0b1)) );
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#ifdef VERILATOR_TRACE
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#ifdef VERILATOR_TRACE
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m_trace->dump(sim_time);
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m_trace->dump(sim_time);
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#endif
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#endif
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