diff --git a/npc/core/src/main/scala/Main.scala b/npc/core/src/main/scala/Main.scala
index c06bc8e..95b9e61 100644
--- a/npc/core/src/main/scala/Main.scala
+++ b/npc/core/src/main/scala/Main.scala
@@ -2,8 +2,10 @@ package npc
 
 import chisel3._
 import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
+import chisel3.util.{SRAM}
 import chisel3.stage.ChiselOption
-import npc.util.KeyboardSegController
+import npc.util.{ KeyboardSegController, RegisterFile }
+import flowpc.components.ProgramCounter
 
 class Switch extends Module {
   val io = IO(new Bundle {
@@ -31,3 +33,12 @@ class Keyboard extends Module {
   io.segs := seg_handler.io.segs
 }
 
+<<<<<<< Updated upstream
+=======
+class Flowpc extends Module {
+  val io = IO(new Bundle { })
+  val register_file = new RegisterFile(readPorts = 2);
+  val pc = new ProgramCounter(32);
+  val adder = new SRAM()
+}
+>>>>>>> Stashed changes
diff --git a/npc/core/src/main/scala/ProgramCounter.scala b/npc/core/src/main/scala/ProgramCounter.scala
new file mode 100644
index 0000000..0687f9a
--- /dev/null
+++ b/npc/core/src/main/scala/ProgramCounter.scala
@@ -0,0 +1,11 @@
+package flowpc.components
+import chisel3._
+import chisel3.util.{Valid}
+
+class ProgramCounter (width: Int) extends Module {
+  val io = new Bundle {
+    val next_pc = Input(Flipped(Valid(UInt(width.W))))
+    val pc = Output(UInt(width.W))
+  }
+    io.pc := Mux(io.next_pc.valid, io.next_pc.bits, io.pc)
+}