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fix(npc): jalr wrong imm

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This commit is contained in:
xinyangli 2024-04-11 09:21:17 +08:00
parent 89847cfdb4
commit 55230247b2
Signed by: xin
SSH key fingerprint: SHA256:qZ/tzd8lYRtUFSrfBDBMcUqV4GHKxqeqRA3huItgvbk
2 changed files with 17 additions and 4 deletions
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2
npc/core/src/main/scala/components/ALU.scala
View file

@ -12,7 +12,7 @@ class ALUControlInterface extends Bundle {
val aSrcARs1, aSrcAPc, aSrcAZero = Value val aSrcARs1, aSrcAPc, aSrcAZero = Value
} }
object SrcBSelect extends ChiselEnum { object SrcBSelect extends ChiselEnum {
val aSrcBRs2, aSrcBImmI, aSrcBImmJ, aSrcBImmB, aSrcBImmS = Value val aSrcBRs2, aSrcBImmI, aSrcBImmJ, aSrcBImmB, aSrcBImmS, aSrcBImmU = Value
} }
val op = Input(OpSelect()) val op = Input(OpSelect())
val srcASelect = Input(SrcASelect()) val srcASelect = Input(SrcASelect())

19
npc/core/src/main/scala/top/FlowMain.scala
View file

@ -130,6 +130,16 @@ class Control(width: Int) extends RawModule {
// Exe | op :: srcASelect :: srcBSelect :: signExt :: HNil // Exe | op :: srcASelect :: srcBSelect :: signExt :: HNil
// Mem | valid :: writeMask :: writeEnable :: HNil // Mem | valid :: writeMask :: writeEnable :: HNil
(lui , (r(true.B) :: r(rAluOut) ::
r(false.B) :: r(pStaticNpc)::
r(aOpAdd) :: r(aSrcAZero) :: r(aSrcBImmU) :: r(false.B) ::
r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)),
(auipc , (r(true.B) :: r(rAluOut) ::
r(false.B) :: r(pStaticNpc)::
r(aOpAdd) :: r(aSrcAPc) :: r(aSrcBImmU) :: r(false.B) ::
r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)),
// ---- Control Transfer Instructions ---- // ---- Control Transfer Instructions ----
(jal , (r(true.B) :: r(rNpc) :: (jal , (r(true.B) :: r(rNpc) ::
r(false.B) :: r(pExeOut) :: r(false.B) :: r(pExeOut) ::
@ -138,7 +148,7 @@ class Control(width: Int) extends RawModule {
(jalr , (r(true.B) :: r(rNpc) :: (jalr , (r(true.B) :: r(rNpc) ::
r(false.B) :: r(pExeOut) :: r(false.B) :: r(pExeOut) ::
r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmJ) :: r(false.B) :: r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: r(false.B) ::
r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)),
(beq , (r(false.B) :: l(WriteSelect) :: (beq , (r(false.B) :: l(WriteSelect) ::
@ -208,7 +218,7 @@ class Control(width: Int) extends RawModule {
(addi , (r(true.B) :: r(rAluOut) :: (addi , (r(true.B) :: r(rAluOut) ::
r(false.B) :: r(pStaticNpc) :: r(false.B) :: r(pStaticNpc) ::
r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) :: r(aOpAdd) :: r(aSrcARs1) :: r(aSrcBImmI) :: l(Bool()) ::
r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)), r(false.B) :: l(UInt(4.W)):: r(false.B) :: HNil)),
(slti , (r(true.B) :: r(rAluOut) :: (slti , (r(true.B) :: r(rAluOut) ::
r(false.B) :: r(pStaticNpc) :: r(false.B) :: r(pStaticNpc) ::
@ -385,10 +395,13 @@ class Flow extends Module {
alu.in.a(lit(aSrcAZero)) := 0.U alu.in.a(lit(aSrcAZero)) := 0.U
alu.in.b(lit(aSrcBRs2)) := reg.out.src(1) alu.in.b(lit(aSrcBRs2)) := reg.out.src(1)
alu.in.b(lit(aSrcBImmI)) := inst(31, 20).pad(aSrcBImmI.getWidth) // alu.in.b(lit(aSrcBImmI)) := inst(31, 20).pad(aSrcBImmI.getWidth)
alu.in.b(lit(aSrcBImmI)) := Cat(Fill(20, inst(31)), inst(31, 20))
alu.in.b(lit(aSrcBImmJ)) := Cat(Fill(12, inst(31)), inst(19, 12), inst(20), inst(30, 25), inst(24, 21), 0.U(1.W)) alu.in.b(lit(aSrcBImmJ)) := Cat(Fill(12, inst(31)), inst(19, 12), inst(20), inst(30, 25), inst(24, 21), 0.U(1.W))
alu.in.b(lit(aSrcBImmB)) := Cat(Fill(20, inst(31)), inst(7), inst(30, 25), inst(11, 8), inst(0)) alu.in.b(lit(aSrcBImmB)) := Cat(Fill(20, inst(31)), inst(7), inst(30, 25), inst(11, 8), inst(0))
alu.in.b(lit(aSrcBImmS)) := Cat(inst(31), inst(19, 12), inst(20), inst(30, 25), inst(24, 21), 0.U(1.W)).pad(aSrcBImmS.getWidth) alu.in.b(lit(aSrcBImmS)) := Cat(inst(31), inst(19, 12), inst(20), inst(30, 25), inst(24, 21), 0.U(1.W)).pad(aSrcBImmS.getWidth)
alu.in.b(lit(aSrcBImmU)) := Cat(inst(31, 12), 0.U(12.W))
printf(cf"inst = $inst\n");
Trace.traceName(pc.out); Trace.traceName(pc.out);
dontTouch(control.out) dontTouch(control.out)