refactor: clean SegControllerGenerator
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parent
674702b552
commit
4a38cb566b
3 changed files with 52 additions and 45 deletions
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@ -53,3 +53,47 @@ class KeyboardController extends Module {
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received := false.B
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}
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}
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class KeyboardSegController extends Module {
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val io = IO(new Bundle{
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val keycode = Flipped(Decoupled(UInt(8.W)))
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val segs = Vec(8, UInt(8.W))
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})
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io.keycode.ready := false.B
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when(io.keycode.valid) {
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io.keycode.ready := true.B
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}
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// 0x1C.U -> 0x41.U, ...
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val keycode_to_ascii = Seq(
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0x1C.U, 0x32.U, 0x21.U, 0x23.U, 0x24.U, 0x2B.U,
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0x34.U, 0x33.U, 0x43.U, 0x3B.U, 0x42.U, 0x4B.U,
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0x3A.U, 0x31.U, 0x44.U, 0x4D.U, 0x15.U, 0x2D.U,
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0x1B.U, 0x2C.U, 0x3C.U, 0x2A.U, 0x1D.U, 0x22.U,
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0x35.U, 0x1A.U, 0x45.U, 0x16.U, 0x1E.U, 0x26.U,
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0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
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).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
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val keycode = RegInit(0.U(8.W))
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val counter = Counter(0xFF)
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val release_state = RegInit(Bool(), false.B)
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when(io.keycode.ready && io.keycode.valid) {
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when(io.keycode.bits === 0xF0.U) {
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release_state := true.B
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}.elsewhen(!release_state) {
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counter.inc()
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keycode := io.keycode.bits
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}.otherwise{
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// Release code on io.keycode.bits
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release_state := false.B
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}
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}
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val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
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val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
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val seg_contoller = Module(new SegControllerGenerator(8, UInt(8.W)))
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seg_contoller.io.in_segs := VecInit(Seq(keycode, ascii, counter.value, 0.U))
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io.segs := seg_contoller.io.segs
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}
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@ -3,6 +3,7 @@ package npc
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import chisel3._
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import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
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import chisel3.stage.ChiselOption
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import npc.util.KeyboardSegController
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class Switch extends Module {
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val io = IO(new Bundle {
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@ -21,7 +22,7 @@ class Keyboard extends Module {
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val segs = Output(Vec(8, UInt(8.W)))
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})
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val seg_handler = Module(new SegControllerGenerator(seg_count = 8))
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val seg_handler = Module(new KeyboardSegController)
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val keyboard_controller = Module(new KeyboardController)
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seg_handler.io.keycode <> keyboard_controller.io.out
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@ -4,59 +4,21 @@ import chisel3._
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import chisel3.util._
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import chisel3.util.log2Ceil
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class SegControllerGenerator(seg_count: Int) extends Module {
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class SegControllerGenerator[T <: Data](seg_count: Int, t: T) extends Module {
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val io = IO(new Bundle {
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val keycode = Flipped(Decoupled(UInt(8.W)))
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val in_segs = Input(Vec(seg_count / ((t.getWidth + 3) / 4), t))
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val segs = Output(Vec(seg_count, UInt(8.W)))
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})
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io.keycode.ready := false.B
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when(io.keycode.valid) {
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io.keycode.ready := true.B
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}
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val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(8.W))))
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val last_keycode = RegInit(0.U(8.W))
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val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq(
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"b00000011".U, "b10011111".U, "b00100101".U, "b00001101".U,
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"b10011001".U, "b01001001".U, "b01000001".U, "b00011111".U,
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"b00000001".U, "b00001001".U, "b00010001".U, "b11000001".U,
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"b01100011".U, "b10000101".U, "b01100001".U, "b01110001".U,
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))
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val vec = io.in_segs.asTypeOf(Vec(seg_count, UInt(4.W)))
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val keycode_to_ascii = Seq(
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0x1C.U, 0x32.U, 0x21.U, 0x23.U, 0x24.U, 0x2B.U,
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0x34.U, 0x33.U, 0x43.U, 0x3B.U, 0x42.U, 0x4B.U,
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0x3A.U, 0x31.U, 0x44.U, 0x4D.U, 0x15.U, 0x2D.U,
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0x1B.U, 0x2C.U, 0x3C.U, 0x2A.U, 0x1D.U, 0x22.U,
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0x35.U, 0x1A.U, 0x45.U, 0x16.U, 0x1E.U, 0x26.U,
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0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
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).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
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val segs = VecInit(Seq.fill(seg_count)(0.U(8.W)))
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segs := vec.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val keycode = RegInit(0.U(8.W))
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val counter = Counter(0xFF)
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val release_state = RegInit(Bool(), false.B)
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when(io.keycode.ready && io.keycode.valid) {
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when(io.keycode.bits === 0xF0.U) {
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release_state := true.B
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}.elsewhen(!release_state) {
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keycode := io.keycode.bits
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counter.inc()
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}.otherwise{
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// Release code on io.keycode.bits
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release_state := false.B
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}
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}
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val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
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val keycode_seg = keycode_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
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val ascii_digits = VecInit(ascii(3,0)) ++ VecInit(ascii(6,4))
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val ascii_seg = ascii_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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val count_digits = VecInit(counter.value(3,0)) ++ VecInit(counter.value(7,4))
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val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
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seg_regs := keycode_seg ++ ascii_seg ++ count_seg ++ Seq(0xFF.U, 0xFF.U)
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io.segs := seg_regs
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io.segs := segs
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}
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