refactor: clean SegControllerGenerator

This commit is contained in:
xinyangli 2024-01-10 21:45:50 +08:00
parent 674702b552
commit 4a38cb566b
No known key found for this signature in database
3 changed files with 52 additions and 45 deletions

View file

@ -53,3 +53,47 @@ class KeyboardController extends Module {
received := false.B
}
}
class KeyboardSegController extends Module {
val io = IO(new Bundle{
val keycode = Flipped(Decoupled(UInt(8.W)))
val segs = Vec(8, UInt(8.W))
})
io.keycode.ready := false.B
when(io.keycode.valid) {
io.keycode.ready := true.B
}
// 0x1C.U -> 0x41.U, ...
val keycode_to_ascii = Seq(
0x1C.U, 0x32.U, 0x21.U, 0x23.U, 0x24.U, 0x2B.U,
0x34.U, 0x33.U, 0x43.U, 0x3B.U, 0x42.U, 0x4B.U,
0x3A.U, 0x31.U, 0x44.U, 0x4D.U, 0x15.U, 0x2D.U,
0x1B.U, 0x2C.U, 0x3C.U, 0x2A.U, 0x1D.U, 0x22.U,
0x35.U, 0x1A.U, 0x45.U, 0x16.U, 0x1E.U, 0x26.U,
0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
val keycode = RegInit(0.U(8.W))
val counter = Counter(0xFF)
val release_state = RegInit(Bool(), false.B)
when(io.keycode.ready && io.keycode.valid) {
when(io.keycode.bits === 0xF0.U) {
release_state := true.B
}.elsewhen(!release_state) {
counter.inc()
keycode := io.keycode.bits
}.otherwise{
// Release code on io.keycode.bits
release_state := false.B
}
}
val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
val seg_contoller = Module(new SegControllerGenerator(8, UInt(8.W)))
seg_contoller.io.in_segs := VecInit(Seq(keycode, ascii, counter.value, 0.U))
io.segs := seg_contoller.io.segs
}

View file

@ -3,6 +3,7 @@ package npc
import chisel3._
import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
import chisel3.stage.ChiselOption
import npc.util.KeyboardSegController
class Switch extends Module {
val io = IO(new Bundle {
@ -21,7 +22,7 @@ class Keyboard extends Module {
val segs = Output(Vec(8, UInt(8.W)))
})
val seg_handler = Module(new SegControllerGenerator(seg_count = 8))
val seg_handler = Module(new KeyboardSegController)
val keyboard_controller = Module(new KeyboardController)
seg_handler.io.keycode <> keyboard_controller.io.out

View file

@ -4,59 +4,21 @@ import chisel3._
import chisel3.util._
import chisel3.util.log2Ceil
class SegControllerGenerator(seg_count: Int) extends Module {
class SegControllerGenerator[T <: Data](seg_count: Int, t: T) extends Module {
val io = IO(new Bundle {
val keycode = Flipped(Decoupled(UInt(8.W)))
val in_segs = Input(Vec(seg_count / ((t.getWidth + 3) / 4), t))
val segs = Output(Vec(seg_count, UInt(8.W)))
})
io.keycode.ready := false.B
when(io.keycode.valid) {
io.keycode.ready := true.B
}
val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(8.W))))
val last_keycode = RegInit(0.U(8.W))
val digit_to_seg = ((0 until 16).map(_.U)).zip(Seq(
"b00000011".U, "b10011111".U, "b00100101".U, "b00001101".U,
"b10011001".U, "b01001001".U, "b01000001".U, "b00011111".U,
"b00000001".U, "b00001001".U, "b00010001".U, "b11000001".U,
"b01100011".U, "b10000101".U, "b01100001".U, "b01110001".U,
))
val vec = io.in_segs.asTypeOf(Vec(seg_count, UInt(4.W)))
val keycode_to_ascii = Seq(
0x1C.U, 0x32.U, 0x21.U, 0x23.U, 0x24.U, 0x2B.U,
0x34.U, 0x33.U, 0x43.U, 0x3B.U, 0x42.U, 0x4B.U,
0x3A.U, 0x31.U, 0x44.U, 0x4D.U, 0x15.U, 0x2D.U,
0x1B.U, 0x2C.U, 0x3C.U, 0x2A.U, 0x1D.U, 0x22.U,
0x35.U, 0x1A.U, 0x45.U, 0x16.U, 0x1E.U, 0x26.U,
0x25.U, 0x2E.U, 0x36.U, 0x3D.U, 0x3E.U, 0x46.U,
).zip(((0x41 to 0x5A) ++ (0x30 to 0x39)).map(_.U))
val segs = VecInit(Seq.fill(seg_count)(0.U(8.W)))
segs := vec.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
val keycode = RegInit(0.U(8.W))
val counter = Counter(0xFF)
val release_state = RegInit(Bool(), false.B)
when(io.keycode.ready && io.keycode.valid) {
when(io.keycode.bits === 0xF0.U) {
release_state := true.B
}.elsewhen(!release_state) {
keycode := io.keycode.bits
counter.inc()
}.otherwise{
// Release code on io.keycode.bits
release_state := false.B
}
}
val keycode_digits = VecInit(keycode(3,0)) ++ VecInit(keycode(7,4))
val keycode_seg = keycode_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
val ascii = MuxLookup(keycode, 0.U)(keycode_to_ascii)
val ascii_digits = VecInit(ascii(3,0)) ++ VecInit(ascii(6,4))
val ascii_seg = ascii_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
val count_digits = VecInit(counter.value(3,0)) ++ VecInit(counter.value(7,4))
val count_seg = count_digits.map(MuxLookup(_, 0xFF.U)(digit_to_seg))
seg_regs := keycode_seg ++ ascii_seg ++ count_seg ++ Seq(0xFF.U, 0xFF.U)
io.segs := seg_regs
io.segs := segs
}