xin/ysyx-workbench
1
0
Fork 0
Code Issues Pull requests 1 Projects Releases Packages Wiki Activity Actions

> configure(npc)

Browse source 
ysyx_22040000 李心杨
 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux
  20:30:51  up 1 day 19:31,  2 users,  load average: 0.75, 0.84, 0.73
This commit is contained in:
tracer-ysyx 2024-01-09 20:30:51 +08:00 committed by xinyangli
parent d02c8f5681
commit 45b0983c4a
No known key found for this signature in database
21 changed files with 290 additions and 780 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
npc/CMakeLists.txt
View file

@ -17,7 +17,7 @@ find_package(verilator REQUIRED)
find_library(NVBOARD_LIBRARY NAMES nvboard) find_library(NVBOARD_LIBRARY NAMES nvboard)
find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h) find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h)
set(TOPMODULE "Switch") set(TOPMODULE "Keyboard")
set(SCALA_CORE "${CMAKE_CURRENT_SOURCE_DIR}/core") set(SCALA_CORE "${CMAKE_CURRENT_SOURCE_DIR}/core")
set(CHISEL_MODULE_CLASS "${CMAKE_PROJECT_NAME}.${TOPMODULE}") set(CHISEL_MODULE_CLASS "${CMAKE_PROJECT_NAME}.${TOPMODULE}")
file(GLOB_RECURSE SCALA_CORE_SOURCES "${SCALA_CORE}/src/main/scala/*.scala") file(GLOB_RECURSE SCALA_CORE_SOURCES "${SCALA_CORE}/src/main/scala/*.scala")

12
npc/constr/Keyboard.nxdc Normal file
View file

@ -0,0 +1,12 @@
top=Keyboard
io_ps2_clk PS2_CLK
io_ps2_data PS2_DAT
io_seg_0 (SEG0A, SEG0B, SEG0C, SEG0D, SEG0E, SEG0F, SEG0G, DEC0P)
io_seg_1 (SEG1A, SEG1B, SEG1C, SEG1D, SEG1E, SEG1F, SEG1G, DEC1P)
io_seg_2 (SEG2A, SEG2B, SEG2C, SEG2D, SEG2E, SEG2F, SEG2G, DEC2P)
io_seg_3 (SEG3A, SEG3B, SEG3C, SEG3D, SEG3E, SEG3F, SEG3G, DEC3P)
io_seg_4 (SEG4A, SEG4B, SEG4C, SEG4D, SEG4E, SEG4F, SEG4G, DEC4P)
io_seg_5 (SEG5A, SEG5B, SEG5C, SEG5D, SEG5E, SEG5F, SEG5G, DEC5P)
io_seg_6 (SEG6A, SEG6B, SEG6C, SEG6D, SEG6E, SEG6F, SEG6G, DEC6P)
io_seg_7 (SEG7A, SEG7B, SEG7C, SEG7D, SEG7E, SEG7F, SEG7G, DEC7P)

13
npc/core/.gitignore vendored Normal file
View file

@ -0,0 +1,13 @@
# Created by https://www.toptal.com/developers/gitignore/api/scala
# Edit at https://www.toptal.com/developers/gitignore?templates=scala
### Scala ###
*.class
*.log
# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
hs_err_pid*
# End of https://www.toptal.com/developers/gitignore/api/scala
test_run_dir/

0
npc/.scalafmt.conf → npc/core/.scalafmt.conf
View file

110
npc/core/src/main/scala/Keyboard.scala Normal file
View file

@ -0,0 +1,110 @@
package npc.keyboard
import chisel3._
import chisel3.util.{Counter, Decoupled, Queue, Reverse, MuxLookup}
import npc.seg._
class PS2Port extends Bundle {
val clk = Input(Bool())
val data = Input(UInt(1.W))
}
object PS2Port {
def apply(): PS2Port = {
new PS2Port
}
}
class KeyboardController extends Module {
val io = IO(new Bundle {
val ps2 = PS2Port()
val out = Decoupled(UInt(8.W))
})
// valid only on the clock negedge of ps2_clk
val ps2_clk_valid = RegNext(io.ps2.clk, false.B) & ~io.ps2.clk
val cycle_counter = Counter(11)
val concated_data = RegInit(0.U(8.W))
val queue_io = Wire(Flipped(Decoupled(UInt(8.W))))
val queue = Queue(queue_io, entries = 8)
val received = RegInit(Bool(), false.B)
val pushed = RegNext(queue_io.valid && queue_io.ready, false.B)
queue_io.valid := false.B
queue_io.bits := Reverse(concated_data)
io.out <> queue
when(cycle_counter.value === 0.U) {
concated_data := 0.U
received := false.B
}
when(ps2_clk_valid) {
when(cycle_counter.value < 9.U && cycle_counter.value >= 1.U) {
concated_data := (concated_data << 1) | io.ps2.data
}.elsewhen(cycle_counter.value === 9.U) {
received := true.B
}
cycle_counter.inc()
}
when(!pushed && received) {
queue_io.valid := true.B
}.elsewhen(pushed && received) {
queue_io.valid := false.B
received := false.B
}
}
class SegHandler(seg_count: Int) extends Module {
val io = IO(new Bundle {
val keycode = Flipped(Decoupled(UInt(8.W)))
val segs = Output(Vec(seg_count, UInt(4.W)))
})
val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(4.W))))
val last_keycode = RegInit(0.U(8.W))
val counter = Counter(0xFF)
val digit_to_seg = Seq(
0.U -> "b0111111".U, // 0
1.U ->"b0000110".U, // 1
2.U -> "b1011011".U, // 2
3.U -> "b1001111".U, // 3
4.U -> "b1100110".U, // 4
5.U -> "b1101101".U, // 5
6.U -> "b1111101".U, // 6
7.U -> "b0000111".U, // 7
8.U -> "b1111111".U, // 8
9.U -> "b1101111".U, // 9
10.U -> "b1110111".U, // A
11.U -> "b1111100".U, // B
12.U -> "b0111001".U, // C
13.U -> "b1011110".U, // D
14.U -> "b1111001".U, // E
15.U -> "b1110001".U // F
)
io.segs := seg_regs
when(io.keycode.valid) {
val data = io.keycode.bits
val state_f0_received = RegNext(data === 0xF0.U, false.B)
io.keycode.ready := true.B
// Handle keycode based on current state
// (keyboard press counter) :: (ASCII code) :: (Keycode)
when(state_f0_received) {
// Release code
}.otherwise{
counter.inc()
last_keycode := io.keycode.bits
}
}.otherwise {
io.keycode.ready := false.B
}
seg_regs := Seq(counter.value, last_keycode, last_keycode).map(d => {
MuxLookup(d & 0xF.U, 0.U)(digit_to_seg) | (MuxLookup((d >> 4.U) & 0xF.U, 0.U)(digit_to_seg) << 4.U)
})
}

33
npc/core/src/main/scala/Main.scala
View file

@ -1,7 +1,7 @@
package npc package npc
import chisel3._ import chisel3._
import chisel3.util.{MuxLookup, Fill} import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
import chisel3.stage.ChiselOption import chisel3.stage.ChiselOption
class RegisterFile(readPorts: Int) extends Module { class RegisterFile(readPorts: Int) extends Module {
@ -56,20 +56,6 @@ class ALUGenerator(width: Int) extends Module {
)) ))
} }
class MuxGenerator(width: Int, nInput: Int) extends Module {
require(width >= 0)
require(nInput >= 1)
require(nInput.toBinaryString.map(_ - '0').sum == 1)
val io = IO(new Bundle {
val in = Input(Vec(nInput, UInt(width.W)))
val sel = Input(UInt(nInput.toBinaryString.reverse.indexOf('1').W))
val out = Output(UInt(width.W))
})
io.out := io.in(io.sel)
}
class Test extends Module { class Test extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val in = Input(UInt(32.W)) val in = Input(UInt(32.W))
@ -93,3 +79,20 @@ class Switch extends Module {
io.out := io.sw(0) ^ io.sw(1) io.out := io.sw(0) ^ io.sw(1)
} }
import npc.keyboard._
class Keyboard extends Module {
val io = IO(new Bundle {
val ps2 = PS2Port()
val segs = Output(Vec(6, UInt(4.W)))
})
val keyboard_controller = new KeyboardController
val seg_handler = new SegHandler(6)
seg_handler.io.keycode <> keyboard_controller.io.out
io <> keyboard_controller.io
io <> seg_handler.io
}

35
npc/core/src/main/scala/SegGenerator.scala Normal file
View file

@ -0,0 +1,35 @@
package npc.seg
import chisel3._
import chisel3.util.{Decoupled}
import chisel3.util.log2Ceil
class SegInput(width: Int) extends Bundle {
require(width > 0)
val addr = UInt(width.W)
val value = UInt(log2Ceil(width).W)
}
object SegInput {
def apply(width: Int): SegInput = {
return new SegInput(width)
}
}
class SegGenerator(width: Int) extends {
val io = IO(new Bundle {
val write = Flipped(Decoupled(SegInput(8)))
val segs = Output(Vec(width, UInt(8.W)))
})
val seg_regs = RegInit(VecInit(Seq.fill(width)(0.U(8.W))))
io.segs := seg_regs
when(io.write.valid) {
val data = io.write.bits
seg_regs(data.addr) := data.value
io.write.ready := true.B
}.otherwise {
io.write.ready := false.B
}
}

64
npc/core/src/test/scala/Keyboard.scala Normal file
View file

@ -0,0 +1,64 @@
package npc.keyboard
import chisel3._
import chiseltest._
import org.scalatest.freespec.AnyFreeSpec
import chiseltest.simulator.WriteVcdAnnotation
class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
def transfer(keycode: Int, clock: Clock, ps2: PS2Port) : Unit = {
require(keycode >= 0 && keycode < 0xFF)
var cycle = 0
var keycode_remain = keycode << 1 // Shift 1 to do nothing at cycle 0
var keycode_collect = 0
ps2.data.poke(1)
ps2.clk.poke(true)
clock.step(1)
for (cycle <- 0 until 9) {
val last_digit = keycode_remain & 1
ps2.clk.poke(true)
ps2.data.poke(last_digit)
clock.step(32)
keycode_collect = keycode_collect | (last_digit << cycle)
keycode_remain = keycode_remain >> 1
ps2.clk.poke(false)
clock.step(32)
}
for (_ <- 9 until 11) {
ps2.clk.poke(true)
clock.step(32)
ps2.clk.poke(false)
clock.step(32)
}
assert(keycode_collect >> 1 == keycode)
clock.step(32)
}
"Simple test" in {
test(new KeyboardController).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
val data = Array(0xE4, 0xD4, 0xC4, 0xA9)
data.foreach(d => {
transfer(d, c.clock, c.io.ps2)
c.io.out.valid.expect(1.U)
c.io.out.bits.expect(d)
c.io.out.ready.poke(1)
c.clock.step(1)
c.io.out.ready.poke(0)
})
data.foreach(d => {
transfer(d, c.clock, c.io.ps2)
})
data.foreach(d => {
c.io.out.valid.expect(1.U)
c.io.out.bits.expect(d)
c.io.out.ready.poke(1)
c.clock.step(1)
c.io.out.ready.poke(0)
})
}
}
"Keyboard Simulation" in {
test(new Keyboard) { c =>
}
}
}

102
npc/core/src/test/scala/Main.scala
View file

@ -3,6 +3,7 @@ package npc
import chisel3._ import chisel3._
import chiseltest._ import chiseltest._
import org.scalatest.freespec.AnyFreeSpec import org.scalatest.freespec.AnyFreeSpec
import chiseltest.simulator.WriteVcdAnnotation
class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester { class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
"RegisterFile should work" - { "RegisterFile should work" - {
@ -41,97 +42,62 @@ class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester { class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
"With 32 width, " - { "With 32 width, " - {
"add should work" in { val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
test(new ALUGenerator(32)) { c => val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
c.io.op.poke(0.U) val mask = BigInt("FFFFFFFF", 16)
c.io.a.poke(5.U) val oprands: List[(BigInt, BigInt)] = List(
c.io.b.poke(3.U) (5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
c.io.out.expect(8.U) )
val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
2 -> ((a, _) => not(a)),
3 -> (_ & _),
4 -> (_ | _),
5 -> (_ ^ _),
6 -> ((a, b) => if (a < b) 1 else 0),
7 -> ((a, b) => if (a == b) 1 else 0),
)
val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
c.io.op.poke(op.U)
oprands.foreach({ case (a, b) =>
c.io.a.poke(a.U)
c.io.b.poke(b.U)
c.io.out.expect(operations(op)(a, b))
})
} }
"add should work" in {
test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
} }
"sub should work" - { "sub should work" - {
"with positive result" in { "with positive result" in {
test(new ALUGenerator(32)) { c => test(new ALUGenerator(32)) { c =>
c.io.op.poke(1.U) validate(c, 1, oprands.filter({case (a, b) => a >= b}))
c.io.a.poke(5.U)
c.io.b.poke(3.U)
c.io.out.expect(2)
} }
} }
"with negative result" in { "with negative result" in {
test(new ALUGenerator(32)) { c => test(new ALUGenerator(32)) { c =>
c.io.op.poke(1.U) validate(c, 1, oprands.filter({case (a, b) => a < b}))
c.io.a.poke(3.U)
c.io.b.poke(5.U)
c.io.out.expect(BigInt("FFFFFFFF", 16) - 1)
} }
} }
} }
"not should work" in { "not should work" in {
test(new ALUGenerator(32)) { c => test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
c.io.op.poke(2.U)
c.io.a.poke(5.U)
c.io.b.poke(3.U)
c.io.out.expect(BigInt("FFFFFFFA", 16))
}
} }
"and should work" in { "and should work" in {
test(new ALUGenerator(32)) { c => test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
c.io.op.poke(3.U)
c.io.a.poke(5.U)
c.io.b.poke(3.U)
c.io.out.expect(1.U)
}
} }
"or should work" in { "or should work" in {
test(new ALUGenerator(32)) { c => test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
c.io.op.poke(4.U)
c.io.a.poke(5.U)
c.io.b.poke(3.U)
c.io.out.expect(7.U)
}
} }
"xor should work" in { "xor should work" in {
test(new ALUGenerator(32)) { c => test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
c.io.op.poke(5.U)
c.io.a.poke(5.U)
c.io.b.poke(3.U)
c.io.out.expect(6.U)
}
} }
"compare should work" in { "compare should work" in {
test(new ALUGenerator(32)) { c => test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
c.io.op.poke(6)
c.io.a.poke(62.U)
c.io.b.poke(3.U)
c.io.out.expect(0.U)
c.io.a.poke(2.U)
c.io.b.poke(103.U)
c.io.out.expect(1.U)
c.io.a.poke(16.U)
c.io.b.poke(16.U)
c.io.out.expect(0.U)
}
} }
"equal should work" in { "equal should work" in {
test(new ALUGenerator(32)) { c => test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
c.io.op.poke(7)
c.io.a.poke(62.U)
c.io.b.poke(3.U)
c.io.out.expect(0.U)
c.io.a.poke(2.U)
c.io.b.poke(103.U)
c.io.out.expect(0.U)
c.io.a.poke(16.U)
c.io.b.poke(16.U)
c.io.out.expect(1.U)
}
} }
} }
} }

276
npc/core/test_run_dir/RegisterFile_should_work_with_2_read_ports/RegisterFile.lo.fir
View file

@ -1,276 +0,0 @@
FIRRTL version 1.2.0
circuit RegisterFile :
module RegisterFile :
input clock : Clock
input reset : UInt<1>
input io_writeEnable : UInt<1> @[core/src/main/scala/Main.scala 9:14]
input io_writeAddr : UInt<5> @[core/src/main/scala/Main.scala 9:14]
input io_writeData : UInt<32> @[core/src/main/scala/Main.scala 9:14]
input io_readAddr_0 : UInt<5> @[core/src/main/scala/Main.scala 9:14]
input io_readAddr_1 : UInt<5> @[core/src/main/scala/Main.scala 9:14]
output io_readData_0 : UInt<32> @[core/src/main/scala/Main.scala 9:14]
output io_readData_1 : UInt<32> @[core/src/main/scala/Main.scala 9:14]
reg regFile_0 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_0) @[core/src/main/scala/Main.scala 17:24]
reg regFile_1 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_1) @[core/src/main/scala/Main.scala 17:24]
reg regFile_2 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_2) @[core/src/main/scala/Main.scala 17:24]
reg regFile_3 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_3) @[core/src/main/scala/Main.scala 17:24]
reg regFile_4 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_4) @[core/src/main/scala/Main.scala 17:24]
reg regFile_5 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_5) @[core/src/main/scala/Main.scala 17:24]
reg regFile_6 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_6) @[core/src/main/scala/Main.scala 17:24]
reg regFile_7 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_7) @[core/src/main/scala/Main.scala 17:24]
reg regFile_8 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_8) @[core/src/main/scala/Main.scala 17:24]
reg regFile_9 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_9) @[core/src/main/scala/Main.scala 17:24]
reg regFile_10 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_10) @[core/src/main/scala/Main.scala 17:24]
reg regFile_11 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_11) @[core/src/main/scala/Main.scala 17:24]
reg regFile_12 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_12) @[core/src/main/scala/Main.scala 17:24]
reg regFile_13 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_13) @[core/src/main/scala/Main.scala 17:24]
reg regFile_14 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_14) @[core/src/main/scala/Main.scala 17:24]
reg regFile_15 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_15) @[core/src/main/scala/Main.scala 17:24]
reg regFile_16 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_16) @[core/src/main/scala/Main.scala 17:24]
reg regFile_17 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_17) @[core/src/main/scala/Main.scala 17:24]
reg regFile_18 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_18) @[core/src/main/scala/Main.scala 17:24]
reg regFile_19 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_19) @[core/src/main/scala/Main.scala 17:24]
reg regFile_20 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_20) @[core/src/main/scala/Main.scala 17:24]
reg regFile_21 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_21) @[core/src/main/scala/Main.scala 17:24]
reg regFile_22 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_22) @[core/src/main/scala/Main.scala 17:24]
reg regFile_23 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_23) @[core/src/main/scala/Main.scala 17:24]
reg regFile_24 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_24) @[core/src/main/scala/Main.scala 17:24]
reg regFile_25 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_25) @[core/src/main/scala/Main.scala 17:24]
reg regFile_26 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_26) @[core/src/main/scala/Main.scala 17:24]
reg regFile_27 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_27) @[core/src/main/scala/Main.scala 17:24]
reg regFile_28 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_28) @[core/src/main/scala/Main.scala 17:24]
reg regFile_29 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_29) @[core/src/main/scala/Main.scala 17:24]
reg regFile_30 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_30) @[core/src/main/scala/Main.scala 17:24]
reg regFile_31 : UInt<32>, clock with :
reset => (UInt<1>("h0"), regFile_31) @[core/src/main/scala/Main.scala 17:24]
node _GEN_0 = validif(eq(UInt<1>("h0"), io_writeAddr), regFile_0) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_1 = mux(eq(UInt<1>("h1"), io_writeAddr), regFile_1, _GEN_0) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_2 = mux(eq(UInt<2>("h2"), io_writeAddr), regFile_2, _GEN_1) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_3 = mux(eq(UInt<2>("h3"), io_writeAddr), regFile_3, _GEN_2) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_4 = mux(eq(UInt<3>("h4"), io_writeAddr), regFile_4, _GEN_3) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_5 = mux(eq(UInt<3>("h5"), io_writeAddr), regFile_5, _GEN_4) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_6 = mux(eq(UInt<3>("h6"), io_writeAddr), regFile_6, _GEN_5) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_7 = mux(eq(UInt<3>("h7"), io_writeAddr), regFile_7, _GEN_6) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_8 = mux(eq(UInt<4>("h8"), io_writeAddr), regFile_8, _GEN_7) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_9 = mux(eq(UInt<4>("h9"), io_writeAddr), regFile_9, _GEN_8) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_10 = mux(eq(UInt<4>("ha"), io_writeAddr), regFile_10, _GEN_9) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_11 = mux(eq(UInt<4>("hb"), io_writeAddr), regFile_11, _GEN_10) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_12 = mux(eq(UInt<4>("hc"), io_writeAddr), regFile_12, _GEN_11) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_13 = mux(eq(UInt<4>("hd"), io_writeAddr), regFile_13, _GEN_12) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_14 = mux(eq(UInt<4>("he"), io_writeAddr), regFile_14, _GEN_13) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_15 = mux(eq(UInt<4>("hf"), io_writeAddr), regFile_15, _GEN_14) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_16 = mux(eq(UInt<5>("h10"), io_writeAddr), regFile_16, _GEN_15) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_17 = mux(eq(UInt<5>("h11"), io_writeAddr), regFile_17, _GEN_16) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_18 = mux(eq(UInt<5>("h12"), io_writeAddr), regFile_18, _GEN_17) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_19 = mux(eq(UInt<5>("h13"), io_writeAddr), regFile_19, _GEN_18) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_20 = mux(eq(UInt<5>("h14"), io_writeAddr), regFile_20, _GEN_19) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_21 = mux(eq(UInt<5>("h15"), io_writeAddr), regFile_21, _GEN_20) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_22 = mux(eq(UInt<5>("h16"), io_writeAddr), regFile_22, _GEN_21) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_23 = mux(eq(UInt<5>("h17"), io_writeAddr), regFile_23, _GEN_22) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_24 = mux(eq(UInt<5>("h18"), io_writeAddr), regFile_24, _GEN_23) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_25 = mux(eq(UInt<5>("h19"), io_writeAddr), regFile_25, _GEN_24) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_26 = mux(eq(UInt<5>("h1a"), io_writeAddr), regFile_26, _GEN_25) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_27 = mux(eq(UInt<5>("h1b"), io_writeAddr), regFile_27, _GEN_26) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_28 = mux(eq(UInt<5>("h1c"), io_writeAddr), regFile_28, _GEN_27) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_29 = mux(eq(UInt<5>("h1d"), io_writeAddr), regFile_29, _GEN_28) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_30 = mux(eq(UInt<5>("h1e"), io_writeAddr), regFile_30, _GEN_29) @[core/src/main/scala/Main.scala 21:{31,31}]
node _GEN_31 = mux(eq(UInt<5>("h1f"), io_writeAddr), regFile_31, _GEN_30) @[core/src/main/scala/Main.scala 21:{31,31}]
node _regFile_io_writeAddr = _GEN_31 @[core/src/main/scala/Main.scala 21:31]
node _regFile_T = mux(io_writeEnable, io_writeData, _regFile_io_writeAddr) @[core/src/main/scala/Main.scala 21:31]
node _regFile_io_writeAddr_0 = _regFile_T @[core/src/main/scala/Main.scala 21:{25,25}]
node _GEN_32 = mux(eq(UInt<1>("h0"), io_writeAddr), _regFile_io_writeAddr_0, regFile_0) @[core/src/main/scala/Main.scala 17:24 21:{25,25}]
node _GEN_33 = mux(eq(UInt<1>("h1"), io_writeAddr), _regFile_io_writeAddr_0, regFile_1) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_34 = mux(eq(UInt<2>("h2"), io_writeAddr), _regFile_io_writeAddr_0, regFile_2) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_35 = mux(eq(UInt<2>("h3"), io_writeAddr), _regFile_io_writeAddr_0, regFile_3) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_36 = mux(eq(UInt<3>("h4"), io_writeAddr), _regFile_io_writeAddr_0, regFile_4) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_37 = mux(eq(UInt<3>("h5"), io_writeAddr), _regFile_io_writeAddr_0, regFile_5) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_38 = mux(eq(UInt<3>("h6"), io_writeAddr), _regFile_io_writeAddr_0, regFile_6) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_39 = mux(eq(UInt<3>("h7"), io_writeAddr), _regFile_io_writeAddr_0, regFile_7) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_40 = mux(eq(UInt<4>("h8"), io_writeAddr), _regFile_io_writeAddr_0, regFile_8) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_41 = mux(eq(UInt<4>("h9"), io_writeAddr), _regFile_io_writeAddr_0, regFile_9) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_42 = mux(eq(UInt<4>("ha"), io_writeAddr), _regFile_io_writeAddr_0, regFile_10) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_43 = mux(eq(UInt<4>("hb"), io_writeAddr), _regFile_io_writeAddr_0, regFile_11) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_44 = mux(eq(UInt<4>("hc"), io_writeAddr), _regFile_io_writeAddr_0, regFile_12) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_45 = mux(eq(UInt<4>("hd"), io_writeAddr), _regFile_io_writeAddr_0, regFile_13) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_46 = mux(eq(UInt<4>("he"), io_writeAddr), _regFile_io_writeAddr_0, regFile_14) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_47 = mux(eq(UInt<4>("hf"), io_writeAddr), _regFile_io_writeAddr_0, regFile_15) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_48 = mux(eq(UInt<5>("h10"), io_writeAddr), _regFile_io_writeAddr_0, regFile_16) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_49 = mux(eq(UInt<5>("h11"), io_writeAddr), _regFile_io_writeAddr_0, regFile_17) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_50 = mux(eq(UInt<5>("h12"), io_writeAddr), _regFile_io_writeAddr_0, regFile_18) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_51 = mux(eq(UInt<5>("h13"), io_writeAddr), _regFile_io_writeAddr_0, regFile_19) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_52 = mux(eq(UInt<5>("h14"), io_writeAddr), _regFile_io_writeAddr_0, regFile_20) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_53 = mux(eq(UInt<5>("h15"), io_writeAddr), _regFile_io_writeAddr_0, regFile_21) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_54 = mux(eq(UInt<5>("h16"), io_writeAddr), _regFile_io_writeAddr_0, regFile_22) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_55 = mux(eq(UInt<5>("h17"), io_writeAddr), _regFile_io_writeAddr_0, regFile_23) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_56 = mux(eq(UInt<5>("h18"), io_writeAddr), _regFile_io_writeAddr_0, regFile_24) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_57 = mux(eq(UInt<5>("h19"), io_writeAddr), _regFile_io_writeAddr_0, regFile_25) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_58 = mux(eq(UInt<5>("h1a"), io_writeAddr), _regFile_io_writeAddr_0, regFile_26) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_59 = mux(eq(UInt<5>("h1b"), io_writeAddr), _regFile_io_writeAddr_0, regFile_27) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_60 = mux(eq(UInt<5>("h1c"), io_writeAddr), _regFile_io_writeAddr_0, regFile_28) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_61 = mux(eq(UInt<5>("h1d"), io_writeAddr), _regFile_io_writeAddr_0, regFile_29) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_62 = mux(eq(UInt<5>("h1e"), io_writeAddr), _regFile_io_writeAddr_0, regFile_30) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_63 = mux(eq(UInt<5>("h1f"), io_writeAddr), _regFile_io_writeAddr_0, regFile_31) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
node _GEN_64 = validif(eq(UInt<1>("h0"), io_readAddr_0), regFile_0) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_65 = mux(eq(UInt<1>("h1"), io_readAddr_0), regFile_1, _GEN_64) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_66 = mux(eq(UInt<2>("h2"), io_readAddr_0), regFile_2, _GEN_65) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_67 = mux(eq(UInt<2>("h3"), io_readAddr_0), regFile_3, _GEN_66) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_68 = mux(eq(UInt<3>("h4"), io_readAddr_0), regFile_4, _GEN_67) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_69 = mux(eq(UInt<3>("h5"), io_readAddr_0), regFile_5, _GEN_68) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_70 = mux(eq(UInt<3>("h6"), io_readAddr_0), regFile_6, _GEN_69) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_71 = mux(eq(UInt<3>("h7"), io_readAddr_0), regFile_7, _GEN_70) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_72 = mux(eq(UInt<4>("h8"), io_readAddr_0), regFile_8, _GEN_71) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_73 = mux(eq(UInt<4>("h9"), io_readAddr_0), regFile_9, _GEN_72) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_74 = mux(eq(UInt<4>("ha"), io_readAddr_0), regFile_10, _GEN_73) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_75 = mux(eq(UInt<4>("hb"), io_readAddr_0), regFile_11, _GEN_74) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_76 = mux(eq(UInt<4>("hc"), io_readAddr_0), regFile_12, _GEN_75) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_77 = mux(eq(UInt<4>("hd"), io_readAddr_0), regFile_13, _GEN_76) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_78 = mux(eq(UInt<4>("he"), io_readAddr_0), regFile_14, _GEN_77) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_79 = mux(eq(UInt<4>("hf"), io_readAddr_0), regFile_15, _GEN_78) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_80 = mux(eq(UInt<5>("h10"), io_readAddr_0), regFile_16, _GEN_79) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_81 = mux(eq(UInt<5>("h11"), io_readAddr_0), regFile_17, _GEN_80) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_82 = mux(eq(UInt<5>("h12"), io_readAddr_0), regFile_18, _GEN_81) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_83 = mux(eq(UInt<5>("h13"), io_readAddr_0), regFile_19, _GEN_82) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_84 = mux(eq(UInt<5>("h14"), io_readAddr_0), regFile_20, _GEN_83) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_85 = mux(eq(UInt<5>("h15"), io_readAddr_0), regFile_21, _GEN_84) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_86 = mux(eq(UInt<5>("h16"), io_readAddr_0), regFile_22, _GEN_85) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_87 = mux(eq(UInt<5>("h17"), io_readAddr_0), regFile_23, _GEN_86) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_88 = mux(eq(UInt<5>("h18"), io_readAddr_0), regFile_24, _GEN_87) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_89 = mux(eq(UInt<5>("h19"), io_readAddr_0), regFile_25, _GEN_88) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_90 = mux(eq(UInt<5>("h1a"), io_readAddr_0), regFile_26, _GEN_89) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_91 = mux(eq(UInt<5>("h1b"), io_readAddr_0), regFile_27, _GEN_90) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_92 = mux(eq(UInt<5>("h1c"), io_readAddr_0), regFile_28, _GEN_91) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_93 = mux(eq(UInt<5>("h1d"), io_readAddr_0), regFile_29, _GEN_92) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_94 = mux(eq(UInt<5>("h1e"), io_readAddr_0), regFile_30, _GEN_93) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_95 = mux(eq(UInt<5>("h1f"), io_readAddr_0), regFile_31, _GEN_94) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_96 = validif(eq(UInt<1>("h0"), io_readAddr_1), regFile_0) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_97 = mux(eq(UInt<1>("h1"), io_readAddr_1), regFile_1, _GEN_96) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_98 = mux(eq(UInt<2>("h2"), io_readAddr_1), regFile_2, _GEN_97) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_99 = mux(eq(UInt<2>("h3"), io_readAddr_1), regFile_3, _GEN_98) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_100 = mux(eq(UInt<3>("h4"), io_readAddr_1), regFile_4, _GEN_99) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_101 = mux(eq(UInt<3>("h5"), io_readAddr_1), regFile_5, _GEN_100) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_102 = mux(eq(UInt<3>("h6"), io_readAddr_1), regFile_6, _GEN_101) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_103 = mux(eq(UInt<3>("h7"), io_readAddr_1), regFile_7, _GEN_102) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_104 = mux(eq(UInt<4>("h8"), io_readAddr_1), regFile_8, _GEN_103) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_105 = mux(eq(UInt<4>("h9"), io_readAddr_1), regFile_9, _GEN_104) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_106 = mux(eq(UInt<4>("ha"), io_readAddr_1), regFile_10, _GEN_105) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_107 = mux(eq(UInt<4>("hb"), io_readAddr_1), regFile_11, _GEN_106) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_108 = mux(eq(UInt<4>("hc"), io_readAddr_1), regFile_12, _GEN_107) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_109 = mux(eq(UInt<4>("hd"), io_readAddr_1), regFile_13, _GEN_108) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_110 = mux(eq(UInt<4>("he"), io_readAddr_1), regFile_14, _GEN_109) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_111 = mux(eq(UInt<4>("hf"), io_readAddr_1), regFile_15, _GEN_110) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_112 = mux(eq(UInt<5>("h10"), io_readAddr_1), regFile_16, _GEN_111) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_113 = mux(eq(UInt<5>("h11"), io_readAddr_1), regFile_17, _GEN_112) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_114 = mux(eq(UInt<5>("h12"), io_readAddr_1), regFile_18, _GEN_113) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_115 = mux(eq(UInt<5>("h13"), io_readAddr_1), regFile_19, _GEN_114) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_116 = mux(eq(UInt<5>("h14"), io_readAddr_1), regFile_20, _GEN_115) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_117 = mux(eq(UInt<5>("h15"), io_readAddr_1), regFile_21, _GEN_116) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_118 = mux(eq(UInt<5>("h16"), io_readAddr_1), regFile_22, _GEN_117) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_119 = mux(eq(UInt<5>("h17"), io_readAddr_1), regFile_23, _GEN_118) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_120 = mux(eq(UInt<5>("h18"), io_readAddr_1), regFile_24, _GEN_119) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_121 = mux(eq(UInt<5>("h19"), io_readAddr_1), regFile_25, _GEN_120) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_122 = mux(eq(UInt<5>("h1a"), io_readAddr_1), regFile_26, _GEN_121) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_123 = mux(eq(UInt<5>("h1b"), io_readAddr_1), regFile_27, _GEN_122) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_124 = mux(eq(UInt<5>("h1c"), io_readAddr_1), regFile_28, _GEN_123) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_125 = mux(eq(UInt<5>("h1d"), io_readAddr_1), regFile_29, _GEN_124) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_126 = mux(eq(UInt<5>("h1e"), io_readAddr_1), regFile_30, _GEN_125) @[core/src/main/scala/Main.scala 25:{20,20}]
node _GEN_127 = mux(eq(UInt<5>("h1f"), io_readAddr_1), regFile_31, _GEN_126) @[core/src/main/scala/Main.scala 25:{20,20}]
node _regFile_WIRE_0 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_1 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_2 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_3 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_4 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_5 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_6 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_7 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_8 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_9 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_10 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_11 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_12 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_13 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_14 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_15 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_16 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_17 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_18 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_19 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_20 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_21 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_22 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_23 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_24 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_25 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_26 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_27 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_28 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_29 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_30 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_WIRE_31 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
node _regFile_io_readAddr_0 = _GEN_95 @[core/src/main/scala/Main.scala 25:20]
node _regFile_io_readAddr_1 = _GEN_127 @[core/src/main/scala/Main.scala 25:20]
io_readData_0 <= _regFile_io_readAddr_0 @[core/src/main/scala/Main.scala 25:20]
io_readData_1 <= _regFile_io_readAddr_1 @[core/src/main/scala/Main.scala 25:20]
regFile_0 <= mux(reset, _regFile_WIRE_0, UInt<1>("h0")) @[core/src/main/scala/Main.scala 17:{24,24} 22:14]
regFile_1 <= mux(reset, _regFile_WIRE_1, _GEN_33) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_2 <= mux(reset, _regFile_WIRE_2, _GEN_34) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_3 <= mux(reset, _regFile_WIRE_3, _GEN_35) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_4 <= mux(reset, _regFile_WIRE_4, _GEN_36) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_5 <= mux(reset, _regFile_WIRE_5, _GEN_37) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_6 <= mux(reset, _regFile_WIRE_6, _GEN_38) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_7 <= mux(reset, _regFile_WIRE_7, _GEN_39) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_8 <= mux(reset, _regFile_WIRE_8, _GEN_40) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_9 <= mux(reset, _regFile_WIRE_9, _GEN_41) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_10 <= mux(reset, _regFile_WIRE_10, _GEN_42) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_11 <= mux(reset, _regFile_WIRE_11, _GEN_43) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_12 <= mux(reset, _regFile_WIRE_12, _GEN_44) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_13 <= mux(reset, _regFile_WIRE_13, _GEN_45) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_14 <= mux(reset, _regFile_WIRE_14, _GEN_46) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_15 <= mux(reset, _regFile_WIRE_15, _GEN_47) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_16 <= mux(reset, _regFile_WIRE_16, _GEN_48) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_17 <= mux(reset, _regFile_WIRE_17, _GEN_49) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_18 <= mux(reset, _regFile_WIRE_18, _GEN_50) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_19 <= mux(reset, _regFile_WIRE_19, _GEN_51) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_20 <= mux(reset, _regFile_WIRE_20, _GEN_52) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_21 <= mux(reset, _regFile_WIRE_21, _GEN_53) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_22 <= mux(reset, _regFile_WIRE_22, _GEN_54) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_23 <= mux(reset, _regFile_WIRE_23, _GEN_55) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_24 <= mux(reset, _regFile_WIRE_24, _GEN_56) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_25 <= mux(reset, _regFile_WIRE_25, _GEN_57) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_26 <= mux(reset, _regFile_WIRE_26, _GEN_58) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_27 <= mux(reset, _regFile_WIRE_27, _GEN_59) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_28 <= mux(reset, _regFile_WIRE_28, _GEN_60) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_29 <= mux(reset, _regFile_WIRE_29, _GEN_61) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_30 <= mux(reset, _regFile_WIRE_30, _GEN_62) @[core/src/main/scala/Main.scala 17:{24,24}]
regFile_31 <= mux(reset, _regFile_WIRE_31, _GEN_63) @[core/src/main/scala/Main.scala 17:{24,24}]

42
npc/core/test_run_dir/With_32_width_add_should_work/ALUGenerator.lo.fir
View file

@ -1,42 +0,0 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

42
npc/core/test_run_dir/With_32_width_and_should_work/ALUGenerator.lo.fir
View file

@ -1,42 +0,0 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

42
npc/core/test_run_dir/With_32_width_compare_should_work/ALUGenerator.lo.fir
View file

@ -1,42 +0,0 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

42
npc/core/test_run_dir/With_32_width_equal_should_work/ALUGenerator.lo.fir
View file

@ -1,42 +0,0 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

42
npc/core/test_run_dir/With_32_width_not_should_work/ALUGenerator.lo.fir
View file

@ -1,42 +0,0 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

42
npc/core/test_run_dir/With_32_width_or_should_work/ALUGenerator.lo.fir
View file

@ -1,42 +0,0 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

42
npc/core/test_run_dir/With_32_width_sub_should_work/ALUGenerator.lo.fir
View file

@ -1,42 +0,0 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

42
npc/core/test_run_dir/With_32_width_sub_should_work_with_negative_result/ALUGenerator.lo.fir
View file

@ -1,42 +0,0 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

42
npc/core/test_run_dir/With_32_width_sub_should_work_with_positive_result/ALUGenerator.lo.fir
View file

@ -1,42 +0,0 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

42
npc/core/test_run_dir/With_32_width_xor_should_work/ALUGenerator.lo.fir
View file

@ -1,42 +0,0 @@
FIRRTL version 1.2.0
circuit ALUGenerator :
module ALUGenerator :
input clock : Clock
input reset : UInt<1>
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]

3
npc/flake.nix
View file

@ -19,8 +19,11 @@
packages = [ packages = [
clang-tools clang-tools
rnix-lsp rnix-lsp
gdb gdb
jre jre
gtkwave
]; ];
inputsFrom = [ self.packages.${system}.default ]; inputsFrom = [ self.packages.${system}.default ];