> configure(npc)
ysyx_22040000 李心杨 Linux calcite 6.1.69 #1-NixOS SMP PREEMPT_DYNAMIC Wed Dec 20 16:00:29 UTC 2023 x86_64 GNU/Linux 20:30:51 up 1 day 19:31, 2 users, load average: 0.75, 0.84, 0.73
This commit is contained in:
tracer-ysyx
parent
d02c8f5681
commit
45b0983c4a
21 changed files with 290 additions and 780 deletions
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@ -17,7 +17,7 @@ find_package(verilator REQUIRED)
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find_library(NVBOARD_LIBRARY NAMES nvboard)
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find_path(NVBOARD_INCLUDE_DIR NAMES nvboard.h)
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set(TOPMODULE "Switch")
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set(TOPMODULE "Keyboard")
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set(SCALA_CORE "${CMAKE_CURRENT_SOURCE_DIR}/core")
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set(CHISEL_MODULE_CLASS "${CMAKE_PROJECT_NAME}.${TOPMODULE}")
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file(GLOB_RECURSE SCALA_CORE_SOURCES "${SCALA_CORE}/src/main/scala/*.scala")
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12
npc/constr/Keyboard.nxdc
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12
npc/constr/Keyboard.nxdc
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@ -0,0 +1,12 @@
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top=Keyboard
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io_ps2_clk PS2_CLK
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io_ps2_data PS2_DAT
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io_seg_0 (SEG0A, SEG0B, SEG0C, SEG0D, SEG0E, SEG0F, SEG0G, DEC0P)
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io_seg_1 (SEG1A, SEG1B, SEG1C, SEG1D, SEG1E, SEG1F, SEG1G, DEC1P)
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io_seg_2 (SEG2A, SEG2B, SEG2C, SEG2D, SEG2E, SEG2F, SEG2G, DEC2P)
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io_seg_3 (SEG3A, SEG3B, SEG3C, SEG3D, SEG3E, SEG3F, SEG3G, DEC3P)
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io_seg_4 (SEG4A, SEG4B, SEG4C, SEG4D, SEG4E, SEG4F, SEG4G, DEC4P)
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io_seg_5 (SEG5A, SEG5B, SEG5C, SEG5D, SEG5E, SEG5F, SEG5G, DEC5P)
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io_seg_6 (SEG6A, SEG6B, SEG6C, SEG6D, SEG6E, SEG6F, SEG6G, DEC6P)
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io_seg_7 (SEG7A, SEG7B, SEG7C, SEG7D, SEG7E, SEG7F, SEG7G, DEC7P)
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13
npc/core/.gitignore
vendored
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13
npc/core/.gitignore
vendored
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@ -0,0 +1,13 @@
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# Created by https://www.toptal.com/developers/gitignore/api/scala
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# Edit at https://www.toptal.com/developers/gitignore?templates=scala
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### Scala ###
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*.class
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*.log
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# virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
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hs_err_pid*
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# End of https://www.toptal.com/developers/gitignore/api/scala
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test_run_dir/
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110
npc/core/src/main/scala/Keyboard.scala
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110
npc/core/src/main/scala/Keyboard.scala
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@ -0,0 +1,110 @@
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package npc.keyboard
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import chisel3._
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import chisel3.util.{Counter, Decoupled, Queue, Reverse, MuxLookup}
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import npc.seg._
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class PS2Port extends Bundle {
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val clk = Input(Bool())
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val data = Input(UInt(1.W))
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}
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object PS2Port {
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def apply(): PS2Port = {
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new PS2Port
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}
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}
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class KeyboardController extends Module {
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val io = IO(new Bundle {
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val ps2 = PS2Port()
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val out = Decoupled(UInt(8.W))
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})
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// valid only on the clock negedge of ps2_clk
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val ps2_clk_valid = RegNext(io.ps2.clk, false.B) & ~io.ps2.clk
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val cycle_counter = Counter(11)
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val concated_data = RegInit(0.U(8.W))
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val queue_io = Wire(Flipped(Decoupled(UInt(8.W))))
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val queue = Queue(queue_io, entries = 8)
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val received = RegInit(Bool(), false.B)
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val pushed = RegNext(queue_io.valid && queue_io.ready, false.B)
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queue_io.valid := false.B
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queue_io.bits := Reverse(concated_data)
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io.out <> queue
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when(cycle_counter.value === 0.U) {
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concated_data := 0.U
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received := false.B
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}
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when(ps2_clk_valid) {
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when(cycle_counter.value < 9.U && cycle_counter.value >= 1.U) {
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concated_data := (concated_data << 1) | io.ps2.data
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}.elsewhen(cycle_counter.value === 9.U) {
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received := true.B
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}
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cycle_counter.inc()
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}
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when(!pushed && received) {
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queue_io.valid := true.B
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}.elsewhen(pushed && received) {
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queue_io.valid := false.B
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received := false.B
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}
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}
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class SegHandler(seg_count: Int) extends Module {
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val io = IO(new Bundle {
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val keycode = Flipped(Decoupled(UInt(8.W)))
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val segs = Output(Vec(seg_count, UInt(4.W)))
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})
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val seg_regs = RegInit(VecInit(Seq.fill(seg_count)(0.U(4.W))))
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val last_keycode = RegInit(0.U(8.W))
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val counter = Counter(0xFF)
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val digit_to_seg = Seq(
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0.U -> "b0111111".U, // 0
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1.U ->"b0000110".U, // 1
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2.U -> "b1011011".U, // 2
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3.U -> "b1001111".U, // 3
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4.U -> "b1100110".U, // 4
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5.U -> "b1101101".U, // 5
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6.U -> "b1111101".U, // 6
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7.U -> "b0000111".U, // 7
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8.U -> "b1111111".U, // 8
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9.U -> "b1101111".U, // 9
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10.U -> "b1110111".U, // A
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11.U -> "b1111100".U, // B
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12.U -> "b0111001".U, // C
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13.U -> "b1011110".U, // D
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14.U -> "b1111001".U, // E
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15.U -> "b1110001".U // F
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)
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io.segs := seg_regs
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when(io.keycode.valid) {
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val data = io.keycode.bits
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val state_f0_received = RegNext(data === 0xF0.U, false.B)
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io.keycode.ready := true.B
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// Handle keycode based on current state
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// (keyboard press counter) :: (ASCII code) :: (Keycode)
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when(state_f0_received) {
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// Release code
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}.otherwise{
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counter.inc()
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last_keycode := io.keycode.bits
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}
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}.otherwise {
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io.keycode.ready := false.B
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}
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seg_regs := Seq(counter.value, last_keycode, last_keycode).map(d => {
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MuxLookup(d & 0xF.U, 0.U)(digit_to_seg) | (MuxLookup((d >> 4.U) & 0xF.U, 0.U)(digit_to_seg) << 4.U)
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})
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}
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@ -1,7 +1,7 @@
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package npc
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import chisel3._
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import chisel3.util.{MuxLookup, Fill}
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import chisel3.util.{MuxLookup, Fill, Decoupled, Counter, Queue, Reverse}
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import chisel3.stage.ChiselOption
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class RegisterFile(readPorts: Int) extends Module {
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@ -56,20 +56,6 @@ class ALUGenerator(width: Int) extends Module {
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))
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}
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class MuxGenerator(width: Int, nInput: Int) extends Module {
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require(width >= 0)
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require(nInput >= 1)
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require(nInput.toBinaryString.map(_ - '0').sum == 1)
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val io = IO(new Bundle {
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val in = Input(Vec(nInput, UInt(width.W)))
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val sel = Input(UInt(nInput.toBinaryString.reverse.indexOf('1').W))
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val out = Output(UInt(width.W))
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})
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io.out := io.in(io.sel)
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}
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class Test extends Module {
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val io = IO(new Bundle {
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val in = Input(UInt(32.W))
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@ -93,3 +79,20 @@ class Switch extends Module {
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io.out := io.sw(0) ^ io.sw(1)
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}
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import npc.keyboard._
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class Keyboard extends Module {
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val io = IO(new Bundle {
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val ps2 = PS2Port()
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val segs = Output(Vec(6, UInt(4.W)))
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})
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val keyboard_controller = new KeyboardController
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val seg_handler = new SegHandler(6)
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seg_handler.io.keycode <> keyboard_controller.io.out
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io <> keyboard_controller.io
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io <> seg_handler.io
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}
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35
npc/core/src/main/scala/SegGenerator.scala
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35
npc/core/src/main/scala/SegGenerator.scala
Normal file
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@ -0,0 +1,35 @@
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package npc.seg
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import chisel3._
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import chisel3.util.{Decoupled}
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import chisel3.util.log2Ceil
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class SegInput(width: Int) extends Bundle {
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require(width > 0)
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val addr = UInt(width.W)
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val value = UInt(log2Ceil(width).W)
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}
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object SegInput {
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def apply(width: Int): SegInput = {
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return new SegInput(width)
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}
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}
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class SegGenerator(width: Int) extends {
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val io = IO(new Bundle {
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val write = Flipped(Decoupled(SegInput(8)))
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val segs = Output(Vec(width, UInt(8.W)))
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})
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val seg_regs = RegInit(VecInit(Seq.fill(width)(0.U(8.W))))
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io.segs := seg_regs
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when(io.write.valid) {
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val data = io.write.bits
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seg_regs(data.addr) := data.value
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io.write.ready := true.B
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}.otherwise {
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io.write.ready := false.B
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}
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}
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64
npc/core/src/test/scala/Keyboard.scala
Normal file
64
npc/core/src/test/scala/Keyboard.scala
Normal file
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@ -0,0 +1,64 @@
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package npc.keyboard
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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import chiseltest.simulator.WriteVcdAnnotation
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class KeyboardControllerSpec extends AnyFreeSpec with ChiselScalatestTester {
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def transfer(keycode: Int, clock: Clock, ps2: PS2Port) : Unit = {
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require(keycode >= 0 && keycode < 0xFF)
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var cycle = 0
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var keycode_remain = keycode << 1 // Shift 1 to do nothing at cycle 0
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var keycode_collect = 0
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ps2.data.poke(1)
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ps2.clk.poke(true)
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clock.step(1)
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for (cycle <- 0 until 9) {
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val last_digit = keycode_remain & 1
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ps2.clk.poke(true)
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ps2.data.poke(last_digit)
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clock.step(32)
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keycode_collect = keycode_collect | (last_digit << cycle)
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keycode_remain = keycode_remain >> 1
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ps2.clk.poke(false)
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clock.step(32)
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}
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for (_ <- 9 until 11) {
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ps2.clk.poke(true)
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clock.step(32)
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ps2.clk.poke(false)
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clock.step(32)
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}
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assert(keycode_collect >> 1 == keycode)
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clock.step(32)
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}
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"Simple test" in {
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test(new KeyboardController).withAnnotations(Seq(WriteVcdAnnotation)) { c =>
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val data = Array(0xE4, 0xD4, 0xC4, 0xA9)
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data.foreach(d => {
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transfer(d, c.clock, c.io.ps2)
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c.io.out.valid.expect(1.U)
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c.io.out.bits.expect(d)
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c.io.out.ready.poke(1)
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c.clock.step(1)
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c.io.out.ready.poke(0)
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})
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data.foreach(d => {
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transfer(d, c.clock, c.io.ps2)
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})
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data.foreach(d => {
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c.io.out.valid.expect(1.U)
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c.io.out.bits.expect(d)
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c.io.out.ready.poke(1)
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c.clock.step(1)
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c.io.out.ready.poke(0)
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})
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}
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}
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"Keyboard Simulation" in {
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test(new Keyboard) { c =>
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}
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}
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}
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@ -3,6 +3,7 @@ package npc
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import chisel3._
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import chiseltest._
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import org.scalatest.freespec.AnyFreeSpec
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import chiseltest.simulator.WriteVcdAnnotation
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class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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"RegisterFile should work" - {
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@ -41,97 +42,62 @@ class RegisterFileSpec extends AnyFreeSpec with ChiselScalatestTester {
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class ALUGeneratorSpec extends AnyFreeSpec with ChiselScalatestTester {
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"With 32 width, " - {
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val neg = (x: BigInt) => BigInt("FFFFFFFF", 16) - x + 1
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val not = (x: BigInt) => x ^ BigInt("FFFFFFFF", 16)
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val mask = BigInt("FFFFFFFF", 16)
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val oprands: List[(BigInt, BigInt)] = List(
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(5, 3), (101010, 101010), (0xFFFFFFFCL, 0xFFFFFFFFL), (4264115, 2)
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)
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val operations: Map[Int, (BigInt, BigInt) => BigInt] = Map(
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0 -> ((a: BigInt, b: BigInt) => (a + b) & mask),
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1 -> ((a: BigInt, b: BigInt) => (a + neg(b)) & mask),
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2 -> ((a, _) => not(a)),
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3 -> (_ & _),
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4 -> (_ | _),
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5 -> (_ ^ _),
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6 -> ((a, b) => if (a < b) 1 else 0),
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7 -> ((a, b) => if (a == b) 1 else 0),
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)
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val validate = (c: ALUGenerator,op: Int, oprands: List[(BigInt, BigInt)]) => {
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c.io.op.poke(op.U)
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oprands.foreach({ case (a, b) =>
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c.io.a.poke(a.U)
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c.io.b.poke(b.U)
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c.io.out.expect(operations(op)(a, b))
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})
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}
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"add should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(0.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(8.U)
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}
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test(new ALUGenerator(32)) { c => validate(c, 0, oprands) }
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}
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"sub should work" - {
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"with positive result" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(1.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(2)
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validate(c, 1, oprands.filter({case (a, b) => a >= b}))
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}
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}
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"with negative result" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(1.U)
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c.io.a.poke(3.U)
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c.io.b.poke(5.U)
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c.io.out.expect(BigInt("FFFFFFFF", 16) - 1)
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validate(c, 1, oprands.filter({case (a, b) => a < b}))
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}
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}
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}
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"not should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(2.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(BigInt("FFFFFFFA", 16))
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}
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test(new ALUGenerator(32)) { c => validate(c, 2, oprands) }
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}
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"and should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(3.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(1.U)
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}
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test(new ALUGenerator(32)) { c => validate(c, 3, oprands) }
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}
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"or should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(4.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(7.U)
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}
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test(new ALUGenerator(32)) { c => validate(c, 4, oprands) }
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}
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"xor should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(5.U)
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c.io.a.poke(5.U)
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c.io.b.poke(3.U)
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c.io.out.expect(6.U)
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}
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test(new ALUGenerator(32)) { c => validate(c, 5, oprands) }
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}
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"compare should work" in {
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test(new ALUGenerator(32)) { c =>
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c.io.op.poke(6)
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c.io.a.poke(62.U)
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c.io.b.poke(3.U)
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c.io.out.expect(0.U)
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c.io.a.poke(2.U)
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c.io.b.poke(103.U)
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c.io.out.expect(1.U)
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c.io.a.poke(16.U)
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||||
c.io.b.poke(16.U)
|
||||
c.io.out.expect(0.U)
|
||||
}
|
||||
test(new ALUGenerator(32)) { c => validate(c, 6, oprands) }
|
||||
}
|
||||
"equal should work" in {
|
||||
test(new ALUGenerator(32)) { c =>
|
||||
c.io.op.poke(7)
|
||||
|
||||
c.io.a.poke(62.U)
|
||||
c.io.b.poke(3.U)
|
||||
c.io.out.expect(0.U)
|
||||
|
||||
c.io.a.poke(2.U)
|
||||
c.io.b.poke(103.U)
|
||||
c.io.out.expect(0.U)
|
||||
|
||||
c.io.a.poke(16.U)
|
||||
c.io.b.poke(16.U)
|
||||
c.io.out.expect(1.U)
|
||||
}
|
||||
test(new ALUGenerator(32)) { c => validate(c, 7, oprands) }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,276 +0,0 @@
|
|||
FIRRTL version 1.2.0
|
||||
circuit RegisterFile :
|
||||
module RegisterFile :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input io_writeEnable : UInt<1> @[core/src/main/scala/Main.scala 9:14]
|
||||
input io_writeAddr : UInt<5> @[core/src/main/scala/Main.scala 9:14]
|
||||
input io_writeData : UInt<32> @[core/src/main/scala/Main.scala 9:14]
|
||||
input io_readAddr_0 : UInt<5> @[core/src/main/scala/Main.scala 9:14]
|
||||
input io_readAddr_1 : UInt<5> @[core/src/main/scala/Main.scala 9:14]
|
||||
output io_readData_0 : UInt<32> @[core/src/main/scala/Main.scala 9:14]
|
||||
output io_readData_1 : UInt<32> @[core/src/main/scala/Main.scala 9:14]
|
||||
|
||||
reg regFile_0 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_0) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_1 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_1) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_2 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_2) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_3 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_3) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_4 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_4) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_5 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_5) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_6 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_6) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_7 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_7) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_8 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_8) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_9 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_9) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_10 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_10) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_11 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_11) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_12 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_12) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_13 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_13) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_14 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_14) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_15 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_15) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_16 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_16) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_17 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_17) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_18 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_18) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_19 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_19) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_20 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_20) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_21 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_21) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_22 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_22) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_23 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_23) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_24 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_24) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_25 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_25) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_26 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_26) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_27 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_27) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_28 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_28) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_29 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_29) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_30 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_30) @[core/src/main/scala/Main.scala 17:24]
|
||||
reg regFile_31 : UInt<32>, clock with :
|
||||
reset => (UInt<1>("h0"), regFile_31) @[core/src/main/scala/Main.scala 17:24]
|
||||
node _GEN_0 = validif(eq(UInt<1>("h0"), io_writeAddr), regFile_0) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_1 = mux(eq(UInt<1>("h1"), io_writeAddr), regFile_1, _GEN_0) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_2 = mux(eq(UInt<2>("h2"), io_writeAddr), regFile_2, _GEN_1) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_3 = mux(eq(UInt<2>("h3"), io_writeAddr), regFile_3, _GEN_2) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_4 = mux(eq(UInt<3>("h4"), io_writeAddr), regFile_4, _GEN_3) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_5 = mux(eq(UInt<3>("h5"), io_writeAddr), regFile_5, _GEN_4) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_6 = mux(eq(UInt<3>("h6"), io_writeAddr), regFile_6, _GEN_5) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_7 = mux(eq(UInt<3>("h7"), io_writeAddr), regFile_7, _GEN_6) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_8 = mux(eq(UInt<4>("h8"), io_writeAddr), regFile_8, _GEN_7) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_9 = mux(eq(UInt<4>("h9"), io_writeAddr), regFile_9, _GEN_8) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_10 = mux(eq(UInt<4>("ha"), io_writeAddr), regFile_10, _GEN_9) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_11 = mux(eq(UInt<4>("hb"), io_writeAddr), regFile_11, _GEN_10) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_12 = mux(eq(UInt<4>("hc"), io_writeAddr), regFile_12, _GEN_11) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_13 = mux(eq(UInt<4>("hd"), io_writeAddr), regFile_13, _GEN_12) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_14 = mux(eq(UInt<4>("he"), io_writeAddr), regFile_14, _GEN_13) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_15 = mux(eq(UInt<4>("hf"), io_writeAddr), regFile_15, _GEN_14) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_16 = mux(eq(UInt<5>("h10"), io_writeAddr), regFile_16, _GEN_15) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_17 = mux(eq(UInt<5>("h11"), io_writeAddr), regFile_17, _GEN_16) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_18 = mux(eq(UInt<5>("h12"), io_writeAddr), regFile_18, _GEN_17) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_19 = mux(eq(UInt<5>("h13"), io_writeAddr), regFile_19, _GEN_18) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_20 = mux(eq(UInt<5>("h14"), io_writeAddr), regFile_20, _GEN_19) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_21 = mux(eq(UInt<5>("h15"), io_writeAddr), regFile_21, _GEN_20) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_22 = mux(eq(UInt<5>("h16"), io_writeAddr), regFile_22, _GEN_21) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_23 = mux(eq(UInt<5>("h17"), io_writeAddr), regFile_23, _GEN_22) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_24 = mux(eq(UInt<5>("h18"), io_writeAddr), regFile_24, _GEN_23) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_25 = mux(eq(UInt<5>("h19"), io_writeAddr), regFile_25, _GEN_24) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_26 = mux(eq(UInt<5>("h1a"), io_writeAddr), regFile_26, _GEN_25) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_27 = mux(eq(UInt<5>("h1b"), io_writeAddr), regFile_27, _GEN_26) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_28 = mux(eq(UInt<5>("h1c"), io_writeAddr), regFile_28, _GEN_27) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_29 = mux(eq(UInt<5>("h1d"), io_writeAddr), regFile_29, _GEN_28) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_30 = mux(eq(UInt<5>("h1e"), io_writeAddr), regFile_30, _GEN_29) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _GEN_31 = mux(eq(UInt<5>("h1f"), io_writeAddr), regFile_31, _GEN_30) @[core/src/main/scala/Main.scala 21:{31,31}]
|
||||
node _regFile_io_writeAddr = _GEN_31 @[core/src/main/scala/Main.scala 21:31]
|
||||
node _regFile_T = mux(io_writeEnable, io_writeData, _regFile_io_writeAddr) @[core/src/main/scala/Main.scala 21:31]
|
||||
node _regFile_io_writeAddr_0 = _regFile_T @[core/src/main/scala/Main.scala 21:{25,25}]
|
||||
node _GEN_32 = mux(eq(UInt<1>("h0"), io_writeAddr), _regFile_io_writeAddr_0, regFile_0) @[core/src/main/scala/Main.scala 17:24 21:{25,25}]
|
||||
node _GEN_33 = mux(eq(UInt<1>("h1"), io_writeAddr), _regFile_io_writeAddr_0, regFile_1) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_34 = mux(eq(UInt<2>("h2"), io_writeAddr), _regFile_io_writeAddr_0, regFile_2) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_35 = mux(eq(UInt<2>("h3"), io_writeAddr), _regFile_io_writeAddr_0, regFile_3) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_36 = mux(eq(UInt<3>("h4"), io_writeAddr), _regFile_io_writeAddr_0, regFile_4) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_37 = mux(eq(UInt<3>("h5"), io_writeAddr), _regFile_io_writeAddr_0, regFile_5) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_38 = mux(eq(UInt<3>("h6"), io_writeAddr), _regFile_io_writeAddr_0, regFile_6) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_39 = mux(eq(UInt<3>("h7"), io_writeAddr), _regFile_io_writeAddr_0, regFile_7) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_40 = mux(eq(UInt<4>("h8"), io_writeAddr), _regFile_io_writeAddr_0, regFile_8) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_41 = mux(eq(UInt<4>("h9"), io_writeAddr), _regFile_io_writeAddr_0, regFile_9) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_42 = mux(eq(UInt<4>("ha"), io_writeAddr), _regFile_io_writeAddr_0, regFile_10) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_43 = mux(eq(UInt<4>("hb"), io_writeAddr), _regFile_io_writeAddr_0, regFile_11) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_44 = mux(eq(UInt<4>("hc"), io_writeAddr), _regFile_io_writeAddr_0, regFile_12) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_45 = mux(eq(UInt<4>("hd"), io_writeAddr), _regFile_io_writeAddr_0, regFile_13) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_46 = mux(eq(UInt<4>("he"), io_writeAddr), _regFile_io_writeAddr_0, regFile_14) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_47 = mux(eq(UInt<4>("hf"), io_writeAddr), _regFile_io_writeAddr_0, regFile_15) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_48 = mux(eq(UInt<5>("h10"), io_writeAddr), _regFile_io_writeAddr_0, regFile_16) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_49 = mux(eq(UInt<5>("h11"), io_writeAddr), _regFile_io_writeAddr_0, regFile_17) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_50 = mux(eq(UInt<5>("h12"), io_writeAddr), _regFile_io_writeAddr_0, regFile_18) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_51 = mux(eq(UInt<5>("h13"), io_writeAddr), _regFile_io_writeAddr_0, regFile_19) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_52 = mux(eq(UInt<5>("h14"), io_writeAddr), _regFile_io_writeAddr_0, regFile_20) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_53 = mux(eq(UInt<5>("h15"), io_writeAddr), _regFile_io_writeAddr_0, regFile_21) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_54 = mux(eq(UInt<5>("h16"), io_writeAddr), _regFile_io_writeAddr_0, regFile_22) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_55 = mux(eq(UInt<5>("h17"), io_writeAddr), _regFile_io_writeAddr_0, regFile_23) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_56 = mux(eq(UInt<5>("h18"), io_writeAddr), _regFile_io_writeAddr_0, regFile_24) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_57 = mux(eq(UInt<5>("h19"), io_writeAddr), _regFile_io_writeAddr_0, regFile_25) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_58 = mux(eq(UInt<5>("h1a"), io_writeAddr), _regFile_io_writeAddr_0, regFile_26) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_59 = mux(eq(UInt<5>("h1b"), io_writeAddr), _regFile_io_writeAddr_0, regFile_27) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_60 = mux(eq(UInt<5>("h1c"), io_writeAddr), _regFile_io_writeAddr_0, regFile_28) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_61 = mux(eq(UInt<5>("h1d"), io_writeAddr), _regFile_io_writeAddr_0, regFile_29) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_62 = mux(eq(UInt<5>("h1e"), io_writeAddr), _regFile_io_writeAddr_0, regFile_30) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_63 = mux(eq(UInt<5>("h1f"), io_writeAddr), _regFile_io_writeAddr_0, regFile_31) @[core/src/main/scala/Main.scala 19:16 21:{25,25}]
|
||||
node _GEN_64 = validif(eq(UInt<1>("h0"), io_readAddr_0), regFile_0) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_65 = mux(eq(UInt<1>("h1"), io_readAddr_0), regFile_1, _GEN_64) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_66 = mux(eq(UInt<2>("h2"), io_readAddr_0), regFile_2, _GEN_65) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_67 = mux(eq(UInt<2>("h3"), io_readAddr_0), regFile_3, _GEN_66) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_68 = mux(eq(UInt<3>("h4"), io_readAddr_0), regFile_4, _GEN_67) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_69 = mux(eq(UInt<3>("h5"), io_readAddr_0), regFile_5, _GEN_68) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_70 = mux(eq(UInt<3>("h6"), io_readAddr_0), regFile_6, _GEN_69) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_71 = mux(eq(UInt<3>("h7"), io_readAddr_0), regFile_7, _GEN_70) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_72 = mux(eq(UInt<4>("h8"), io_readAddr_0), regFile_8, _GEN_71) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_73 = mux(eq(UInt<4>("h9"), io_readAddr_0), regFile_9, _GEN_72) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_74 = mux(eq(UInt<4>("ha"), io_readAddr_0), regFile_10, _GEN_73) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_75 = mux(eq(UInt<4>("hb"), io_readAddr_0), regFile_11, _GEN_74) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_76 = mux(eq(UInt<4>("hc"), io_readAddr_0), regFile_12, _GEN_75) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_77 = mux(eq(UInt<4>("hd"), io_readAddr_0), regFile_13, _GEN_76) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_78 = mux(eq(UInt<4>("he"), io_readAddr_0), regFile_14, _GEN_77) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_79 = mux(eq(UInt<4>("hf"), io_readAddr_0), regFile_15, _GEN_78) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_80 = mux(eq(UInt<5>("h10"), io_readAddr_0), regFile_16, _GEN_79) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_81 = mux(eq(UInt<5>("h11"), io_readAddr_0), regFile_17, _GEN_80) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_82 = mux(eq(UInt<5>("h12"), io_readAddr_0), regFile_18, _GEN_81) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_83 = mux(eq(UInt<5>("h13"), io_readAddr_0), regFile_19, _GEN_82) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_84 = mux(eq(UInt<5>("h14"), io_readAddr_0), regFile_20, _GEN_83) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_85 = mux(eq(UInt<5>("h15"), io_readAddr_0), regFile_21, _GEN_84) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_86 = mux(eq(UInt<5>("h16"), io_readAddr_0), regFile_22, _GEN_85) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_87 = mux(eq(UInt<5>("h17"), io_readAddr_0), regFile_23, _GEN_86) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_88 = mux(eq(UInt<5>("h18"), io_readAddr_0), regFile_24, _GEN_87) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_89 = mux(eq(UInt<5>("h19"), io_readAddr_0), regFile_25, _GEN_88) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_90 = mux(eq(UInt<5>("h1a"), io_readAddr_0), regFile_26, _GEN_89) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_91 = mux(eq(UInt<5>("h1b"), io_readAddr_0), regFile_27, _GEN_90) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_92 = mux(eq(UInt<5>("h1c"), io_readAddr_0), regFile_28, _GEN_91) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_93 = mux(eq(UInt<5>("h1d"), io_readAddr_0), regFile_29, _GEN_92) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_94 = mux(eq(UInt<5>("h1e"), io_readAddr_0), regFile_30, _GEN_93) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_95 = mux(eq(UInt<5>("h1f"), io_readAddr_0), regFile_31, _GEN_94) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_96 = validif(eq(UInt<1>("h0"), io_readAddr_1), regFile_0) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_97 = mux(eq(UInt<1>("h1"), io_readAddr_1), regFile_1, _GEN_96) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_98 = mux(eq(UInt<2>("h2"), io_readAddr_1), regFile_2, _GEN_97) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_99 = mux(eq(UInt<2>("h3"), io_readAddr_1), regFile_3, _GEN_98) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_100 = mux(eq(UInt<3>("h4"), io_readAddr_1), regFile_4, _GEN_99) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_101 = mux(eq(UInt<3>("h5"), io_readAddr_1), regFile_5, _GEN_100) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_102 = mux(eq(UInt<3>("h6"), io_readAddr_1), regFile_6, _GEN_101) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_103 = mux(eq(UInt<3>("h7"), io_readAddr_1), regFile_7, _GEN_102) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_104 = mux(eq(UInt<4>("h8"), io_readAddr_1), regFile_8, _GEN_103) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_105 = mux(eq(UInt<4>("h9"), io_readAddr_1), regFile_9, _GEN_104) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_106 = mux(eq(UInt<4>("ha"), io_readAddr_1), regFile_10, _GEN_105) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_107 = mux(eq(UInt<4>("hb"), io_readAddr_1), regFile_11, _GEN_106) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_108 = mux(eq(UInt<4>("hc"), io_readAddr_1), regFile_12, _GEN_107) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_109 = mux(eq(UInt<4>("hd"), io_readAddr_1), regFile_13, _GEN_108) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_110 = mux(eq(UInt<4>("he"), io_readAddr_1), regFile_14, _GEN_109) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_111 = mux(eq(UInt<4>("hf"), io_readAddr_1), regFile_15, _GEN_110) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_112 = mux(eq(UInt<5>("h10"), io_readAddr_1), regFile_16, _GEN_111) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_113 = mux(eq(UInt<5>("h11"), io_readAddr_1), regFile_17, _GEN_112) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_114 = mux(eq(UInt<5>("h12"), io_readAddr_1), regFile_18, _GEN_113) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_115 = mux(eq(UInt<5>("h13"), io_readAddr_1), regFile_19, _GEN_114) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_116 = mux(eq(UInt<5>("h14"), io_readAddr_1), regFile_20, _GEN_115) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_117 = mux(eq(UInt<5>("h15"), io_readAddr_1), regFile_21, _GEN_116) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_118 = mux(eq(UInt<5>("h16"), io_readAddr_1), regFile_22, _GEN_117) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_119 = mux(eq(UInt<5>("h17"), io_readAddr_1), regFile_23, _GEN_118) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_120 = mux(eq(UInt<5>("h18"), io_readAddr_1), regFile_24, _GEN_119) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_121 = mux(eq(UInt<5>("h19"), io_readAddr_1), regFile_25, _GEN_120) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_122 = mux(eq(UInt<5>("h1a"), io_readAddr_1), regFile_26, _GEN_121) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_123 = mux(eq(UInt<5>("h1b"), io_readAddr_1), regFile_27, _GEN_122) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_124 = mux(eq(UInt<5>("h1c"), io_readAddr_1), regFile_28, _GEN_123) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_125 = mux(eq(UInt<5>("h1d"), io_readAddr_1), regFile_29, _GEN_124) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_126 = mux(eq(UInt<5>("h1e"), io_readAddr_1), regFile_30, _GEN_125) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _GEN_127 = mux(eq(UInt<5>("h1f"), io_readAddr_1), regFile_31, _GEN_126) @[core/src/main/scala/Main.scala 25:{20,20}]
|
||||
node _regFile_WIRE_0 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_1 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_2 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_3 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_4 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_5 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_6 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_7 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_8 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_9 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_10 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_11 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_12 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_13 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_14 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_15 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_16 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_17 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_18 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_19 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_20 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_21 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_22 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_23 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_24 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_25 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_26 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_27 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_28 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_29 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_30 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_WIRE_31 = UInt<32>("h0") @[core/src/main/scala/Main.scala 17:{32,32}]
|
||||
node _regFile_io_readAddr_0 = _GEN_95 @[core/src/main/scala/Main.scala 25:20]
|
||||
node _regFile_io_readAddr_1 = _GEN_127 @[core/src/main/scala/Main.scala 25:20]
|
||||
io_readData_0 <= _regFile_io_readAddr_0 @[core/src/main/scala/Main.scala 25:20]
|
||||
io_readData_1 <= _regFile_io_readAddr_1 @[core/src/main/scala/Main.scala 25:20]
|
||||
regFile_0 <= mux(reset, _regFile_WIRE_0, UInt<1>("h0")) @[core/src/main/scala/Main.scala 17:{24,24} 22:14]
|
||||
regFile_1 <= mux(reset, _regFile_WIRE_1, _GEN_33) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_2 <= mux(reset, _regFile_WIRE_2, _GEN_34) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_3 <= mux(reset, _regFile_WIRE_3, _GEN_35) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_4 <= mux(reset, _regFile_WIRE_4, _GEN_36) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_5 <= mux(reset, _regFile_WIRE_5, _GEN_37) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_6 <= mux(reset, _regFile_WIRE_6, _GEN_38) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_7 <= mux(reset, _regFile_WIRE_7, _GEN_39) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_8 <= mux(reset, _regFile_WIRE_8, _GEN_40) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_9 <= mux(reset, _regFile_WIRE_9, _GEN_41) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_10 <= mux(reset, _regFile_WIRE_10, _GEN_42) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_11 <= mux(reset, _regFile_WIRE_11, _GEN_43) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_12 <= mux(reset, _regFile_WIRE_12, _GEN_44) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_13 <= mux(reset, _regFile_WIRE_13, _GEN_45) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_14 <= mux(reset, _regFile_WIRE_14, _GEN_46) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_15 <= mux(reset, _regFile_WIRE_15, _GEN_47) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_16 <= mux(reset, _regFile_WIRE_16, _GEN_48) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_17 <= mux(reset, _regFile_WIRE_17, _GEN_49) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_18 <= mux(reset, _regFile_WIRE_18, _GEN_50) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_19 <= mux(reset, _regFile_WIRE_19, _GEN_51) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_20 <= mux(reset, _regFile_WIRE_20, _GEN_52) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_21 <= mux(reset, _regFile_WIRE_21, _GEN_53) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_22 <= mux(reset, _regFile_WIRE_22, _GEN_54) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_23 <= mux(reset, _regFile_WIRE_23, _GEN_55) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_24 <= mux(reset, _regFile_WIRE_24, _GEN_56) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_25 <= mux(reset, _regFile_WIRE_25, _GEN_57) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_26 <= mux(reset, _regFile_WIRE_26, _GEN_58) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_27 <= mux(reset, _regFile_WIRE_27, _GEN_59) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_28 <= mux(reset, _regFile_WIRE_28, _GEN_60) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_29 <= mux(reset, _regFile_WIRE_29, _GEN_61) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_30 <= mux(reset, _regFile_WIRE_30, _GEN_62) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
regFile_31 <= mux(reset, _regFile_WIRE_31, _GEN_63) @[core/src/main/scala/Main.scala 17:{24,24}]
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
FIRRTL version 1.2.0
|
||||
circuit ALUGenerator :
|
||||
module ALUGenerator :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
|
||||
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
|
||||
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
|
||||
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
|
||||
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
|
||||
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
|
||||
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
|
||||
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
|
||||
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
|
||||
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
|
||||
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
|
||||
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
|
||||
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
|
||||
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
|
||||
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
|
||||
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
|
||||
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
FIRRTL version 1.2.0
|
||||
circuit ALUGenerator :
|
||||
module ALUGenerator :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
|
||||
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
|
||||
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
|
||||
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
|
||||
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
|
||||
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
|
||||
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
|
||||
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
|
||||
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
|
||||
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
|
||||
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
|
||||
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
|
||||
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
|
||||
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
|
||||
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
|
||||
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
|
||||
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
FIRRTL version 1.2.0
|
||||
circuit ALUGenerator :
|
||||
module ALUGenerator :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
|
||||
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
|
||||
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
|
||||
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
|
||||
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
|
||||
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
|
||||
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
|
||||
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
|
||||
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
|
||||
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
|
||||
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
|
||||
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
|
||||
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
|
||||
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
|
||||
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
|
||||
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
|
||||
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
FIRRTL version 1.2.0
|
||||
circuit ALUGenerator :
|
||||
module ALUGenerator :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
|
||||
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
|
||||
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
|
||||
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
|
||||
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
|
||||
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
|
||||
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
|
||||
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
|
||||
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
|
||||
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
|
||||
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
|
||||
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
|
||||
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
|
||||
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
|
||||
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
|
||||
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
|
||||
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
FIRRTL version 1.2.0
|
||||
circuit ALUGenerator :
|
||||
module ALUGenerator :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
|
||||
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
|
||||
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
|
||||
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
|
||||
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
|
||||
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
|
||||
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
|
||||
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
|
||||
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
|
||||
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
|
||||
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
|
||||
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
|
||||
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
|
||||
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
|
||||
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
|
||||
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
|
||||
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
FIRRTL version 1.2.0
|
||||
circuit ALUGenerator :
|
||||
module ALUGenerator :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
|
||||
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
|
||||
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
|
||||
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
|
||||
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
|
||||
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
|
||||
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
|
||||
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
|
||||
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
|
||||
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
|
||||
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
|
||||
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
|
||||
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
|
||||
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
|
||||
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
|
||||
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
|
||||
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
FIRRTL version 1.2.0
|
||||
circuit ALUGenerator :
|
||||
module ALUGenerator :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
|
||||
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
|
||||
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
|
||||
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
|
||||
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
|
||||
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
|
||||
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
|
||||
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
|
||||
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
|
||||
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
|
||||
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
|
||||
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
|
||||
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
|
||||
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
|
||||
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
|
||||
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
|
||||
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
FIRRTL version 1.2.0
|
||||
circuit ALUGenerator :
|
||||
module ALUGenerator :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
|
||||
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
|
||||
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
|
||||
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
|
||||
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
|
||||
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
|
||||
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
|
||||
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
|
||||
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
|
||||
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
|
||||
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
|
||||
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
|
||||
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
|
||||
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
|
||||
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
|
||||
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
|
||||
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
FIRRTL version 1.2.0
|
||||
circuit ALUGenerator :
|
||||
module ALUGenerator :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
|
||||
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
|
||||
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
|
||||
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
|
||||
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
|
||||
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
|
||||
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
|
||||
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
|
||||
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
|
||||
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
|
||||
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
|
||||
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
|
||||
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
|
||||
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
|
||||
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
|
||||
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
|
||||
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
FIRRTL version 1.2.0
|
||||
circuit ALUGenerator :
|
||||
module ALUGenerator :
|
||||
input clock : Clock
|
||||
input reset : UInt<1>
|
||||
input io_a : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_b : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
input io_op : UInt<4> @[core/src/main/scala/Main.scala 31:14]
|
||||
output io_out : UInt<32> @[core/src/main/scala/Main.scala 31:14]
|
||||
|
||||
node _adder_b_T = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:35]
|
||||
node _adder_b_T_1 = bits(_adder_b_T, 0, 0) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_2 = mux(_adder_b_T_1, UInt<32>("hffffffff"), UInt<32>("h0")) @[core/src/main/scala/Main.scala 38:22]
|
||||
node _adder_b_T_3 = xor(_adder_b_T_2, io_b) @[core/src/main/scala/Main.scala 38:40]
|
||||
node _adder_b_T_4 = bits(io_op, 0, 0) @[core/src/main/scala/Main.scala 38:55]
|
||||
node _adder_b_T_5 = add(_adder_b_T_3, _adder_b_T_4) @[core/src/main/scala/Main.scala 38:48]
|
||||
node adder_b = tail(_adder_b_T_5, 1) @[core/src/main/scala/Main.scala 38:48]
|
||||
node _add_T = add(io_a, adder_b) @[core/src/main/scala/Main.scala 39:18]
|
||||
node add = tail(_add_T, 1) @[core/src/main/scala/Main.scala 39:18]
|
||||
node and = and(io_a, io_b) @[core/src/main/scala/Main.scala 40:18]
|
||||
node not = not(io_a) @[core/src/main/scala/Main.scala 41:13]
|
||||
node or = or(io_a, io_b) @[core/src/main/scala/Main.scala 42:17]
|
||||
node xor = xor(io_a, io_b) @[core/src/main/scala/Main.scala 43:18]
|
||||
node slt = lt(io_a, io_b) @[core/src/main/scala/Main.scala 44:18]
|
||||
node eq = eq(io_a, io_b) @[core/src/main/scala/Main.scala 45:17]
|
||||
node _io_out_T = eq(UInt<1>("h0"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_1 = mux(_io_out_T, add, UInt<1>("h0")) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_2 = eq(UInt<1>("h1"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_3 = mux(_io_out_T_2, add, _io_out_T_1) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_4 = eq(UInt<2>("h2"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_5 = mux(_io_out_T_4, not, _io_out_T_3) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_6 = eq(UInt<2>("h3"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_7 = mux(_io_out_T_6, and, _io_out_T_5) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_8 = eq(UInt<3>("h4"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_9 = mux(_io_out_T_8, or, _io_out_T_7) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_10 = eq(UInt<3>("h5"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_11 = mux(_io_out_T_10, xor, _io_out_T_9) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_12 = eq(UInt<3>("h6"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_13 = mux(_io_out_T_12, slt, _io_out_T_11) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_14 = eq(UInt<3>("h7"), io_op) @[core/src/main/scala/Main.scala 47:34]
|
||||
node _io_out_T_15 = mux(_io_out_T_14, eq, _io_out_T_13) @[core/src/main/scala/Main.scala 47:34]
|
||||
io_out <= _io_out_T_15 @[core/src/main/scala/Main.scala 47:10]
|
||||
|
|
@ -19,8 +19,11 @@
|
|||
packages = [
|
||||
clang-tools
|
||||
rnix-lsp
|
||||
|
||||
gdb
|
||||
jre
|
||||
|
||||
gtkwave
|
||||
];
|
||||
|
||||
inputsFrom = [ self.packages.${system}.default ];
|
||||
|
|
|
|||
Loading…
Reference in a new issue